JEDEC JESD22-A105C-2004 Power and Temperature Cycling《动力和温度周期变化》.pdf
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1、JEDEC STANDARD Power and Temperature Cycling JESD22-A105C (Revision of JESD22-A105-B) JANUARY 2004, Reaffirmed January 2011 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Dire
2、ctors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assis
3、ting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may i
4、nvolve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents a s
5、ound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No claims to be in confo
6、rmance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or refer to www.jedec.org under Standards and Documents
7、for alternative contact information. Published by JEDEC Solid State Technology Association 2011 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individua
8、l agrees not to charge for or resell the resulting material. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. Organizations may obtain permission to reproduce a limited num
9、ber of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards and Documents for alternative contact information. JEDEC Standard No.
10、22-A105C Page 1 Test Method A105C (Revision of A105B) TEST METHOD A105C POWER AND TEMPERATURE CYCLING (From JEDEC Board Ballot JCB-03-70, formulated under the cognizance of the JC-14.1 Subcommittee on Reliability Test Methods for Packaged Devices.) 1 Scope This test method applies to semiconductor d
11、evices that are subjected to temperature excursions and required to power on and off during all temperatures. The power and temperature cycling test is performed to determine the ability of a device to withstand alternate exposures at high and low temperature extremes with operating biases periodica
12、lly applied and removed. It is intended to simulate worst case conditions encountered in typical applications. The power and temperature cycling test is considered destructive. It is intended for device qualification. 2 Terms and definitions 2.1 Temperature cycle time Time between one high temperatu
13、re extreme to the next, or from one low temperature extreme to the next, for a given sample; see Figure 1. 2.2 Ramp rate The rate of temperature increase or decrease per unit of time for the sample(s). Ramp rate should be measured for the linear portion of the profile curve, which is generally the r
14、ange between 10% and 90% of the test condition temperature range; see Figure 1. Note: Ramp rate can be load dependent and should be verified for the load being tested. 2.3 Dwell time The amount of time the sample temperature has exceeded the specified temperature, either the high or the low temperat
15、ure; see Figure 1. 2.4 Power cycle time Time between one power on to the next, or from one power off to the next, for a given sample; see Figure 1. JEDEC Standard No. 22-A105C Page 2 Test Method A105C (Revision of A105B) 2 Terms and definitions (contd) 2.5 Duty cycle, power The ratio of the power-on
16、 time duration per cycle to the total cycle time. NOTE Power duty cycle is usually expressed as a percentage. 3 Apparatus The apparatus required for this test shall consist of a controlled temperature chamber capable of producing the specified temperatures within the specified transition times. Sock
17、ets or other mounting means shall be provided within the chamber so that reliable electrical contact can be made to the device terminals in the specified circuit configuration. Power supplies and biasing networks shall be capable of maintaining the specified operating conditions throughout the testi
18、ng period despite normal variations in line voltages or ambient temperatures. The test circuitry should also be designed so that existence of abnormal or failed devices does not alter the specified conditions for other units on test. Care should be taken to avoid possible damage from transient volta
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