REG NASA-HDBK-8739 23 W CHG 1-2011 NASA COMPLEX ELECTRONICS HANDBOOK FOR ASSURANCE PROFESSIONALS.pdf

1、NASA HANDBOOK NASA-HDBK 8739.23 Baseline with Change 1 National Aeronautics and Space Administration Washington, DC 20546 Baseline approved: 2011-02-16 Change 1 approved: 2011-03-29 NASA COMPLEX ELECTRONICS HANDBOOK FOR ASSURANCE PROFESSIONALS Measurement System Identification: Metric APPROVED FOR P

2、UBLIC RELEASE DISTRIBUTION IS UNLIMITED Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-NASA-HDBK 8739.23 with change 1 2 of 143 Mars Exploration Rover (2003) Provided by IHSNot for ResaleNo reproduction or networking permitted without license from I

3、HS-,-,-NASA-HDBK 8739.23 with change 1 3 of 143 DOCUMENT HISTORY LOG Status Document Revision Approval Date Description Baseline 2011-02-16 Initial Release (JWL4)Change 1 2011-03-29 Editorial correction to page 2 figure caption (JWL4)This document is subject to reviews per Office of Management and B

4、udget Circular A-119, Federal Participation in the Development and Use of Voluntary Standards (02/10/1998) and NPR 7120.4, NASA Engineering and Program/Project Management Policy. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-NASA-HDBK 8739.23 with

5、change 1 4 of 143 This page intentionally left blank. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-NASA-HDBK 8739.23 with change 1 5 of 143 FOREWORD This NASA Handbook (NASA-HDBK) is approved for use by NASA Headquarters and NASA Centers, includin

6、g Component Facilities. This NASA-HDBK may be applied on contracts per contractual documentation as a reference or training publication. Comments and questions concerning the contents of this publication should be referred to the National Aeronautics and Space Administration, Director, Safety and As

7、surance Requirements Division, Office of Safety and Mission Assurance, Washington, DC 20546. Requests for information, corrections, or additions to this NASA-HDBK shall be submitted via “Feedback” in the NASA Technical Standards System at http:/standards.nasa.gov or to National Aeronautics and Space

8、 Administration, Director, Safety and Assurance Requirements Division, Office of Safety and Mission Assurance, Washington, DC 20546. s/ Bryan OConnor February 16, 2011 Bryan OConnor Approval Date Chief, Safety and Mission Assurance The Office of Safety and Mission Assurance would like to recognize K

9、alynnda Berens and Richard Plastow for their work in authoring this publication. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-NASA-HDBK 8739.23 with change 1 6 of 143 This page intentionally left blank. Provided by IHSNot for ResaleNo reproduction

10、 or networking permitted without license from IHS-,-,-NASA-HDBK 8739.23 with change 1 7 of 143 TABLE OF CONTENTS CHAPTER 1. Overview . 11 1.1 Purpose 11 1.2 Scope . 11 1.3 Anticipated Audience 12 1.4 Handbook Layout 12 CHAPTER 2. Reference Documents and Links 13 2.1 Reference Documents 13 2.2 Links

11、14 CHAPTER 3. Definitions and Acronyms . 15 3.1 Definitions . 15 3.2 Acronyms 20 CHAPTER 4. Complex Electronics Overview 23 4.1 Blurring the Hardware/Software Line . 23 4.2 Programmable versus Designable Devices . 25 4.3 Simple Programmable Logic Devices . 27 4.4 Complex Programmable Logic Devices (

12、CPLD) 28 4.5 Field Programmable Gate Array (FPGA) 30 4.6 Application Specific Integrated Circuit (ASIC) 30 4.7 System-on-Chip (SoC) 30 4.8 Concerns and Issues 31 4.9 Summary . 32 CHAPTER 5. Design Process 33 5.1 Overview of the Complex Electronics Design Process . 33 5.2 Requirements and Specificati

13、ons 36 5.3 Design Entry 37 5.4 Abstraction 40 5.5 Hardware Description Languages . 42 5.6 Programming Example 48 5.7 Synthesis 48 5.8 Implementation 53 5.9 Verification 58 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-NASA-HDBK 8739.23 with change

14、1 8 of 143 CHAPTER 6. Process Assurance 64 6.1 Process Assurance Overview 64 6.2 Identifying Complex Electronics . 67 6.3 Process Assurance Activities . 69 CHAPTER 7. Future Trends 79 7.1 Changes in Complex Electronics Design and Verification . 79 7.2 Into the Not so Distant Future . 81 7.3 NASA Ass

15、urance Changes 83 APPENDIX A Examples . 85 A.1 CPLD . 85 A.2 FPGA . 89 A.3 ASIC 95 A.4 SoC 101 A.5 Reconfigurable Computing . 107 APPENDIX B Coding Style Guidelines 112 B.1 Introduction . 112 B.2 Top-Down Design . 112 B.3 Signals and Variables 119 B.4 Packages 122 B.5 Technology-Specific Code (Xilin

16、x) 126 B.6 Coding for Synthesis . 135 LIST OF TABLES Table 1: Complex Electronics Examples . 26 Table 2: Simple PLD Comparisons . 28 Table 3: CE vs. SW Development Phases . 35 Table 4: VHDL vs. Verilog 46 Table 5: FPGA vs. ASIC Comparison . 57 Table 6: Requirement Verification Activities 59 Table 7:

17、 Design Entry Verification Activities . 60 Table 8: Design Synthesis Verification Activities . 60 Table 9: Implementation Verification Activities . 61 Table 10: Testing Verification Activities . 62 Table 11: Simple Complexity Guidelines 68 Provided by IHSNot for ResaleNo reproduction or networking p

18、ermitted without license from IHS-,-,-NASA-HDBK 8739.23 with change 1 9 of 143 LIST OF FIGURES Figure 1: How Complex Electronics Compares 23 Figure 2: Example of PAL Structure . 27 Figure 3: CPLD vs. FPGA Layout 29 Figure 4: SoC Example Configuration 31 Figure 5: CE vs. SW Life Cycles 33 Figure 6: E

19、xample CE Waterfall Development 34 Figure 7: Complex Electronics Design Views 39 Figure 8: Complex Electronics Domains 41 Figure 9: Warning Buzzer Example 41 Figure 10: General HDL Development . 45 Figure 11: AOI VHDL to Verilog Comparison 51 Figure 12: External Programmer . 56 Figure A-1 CPLD . 85

20、Figure A-2 FGPA . 89 Figure A-3 ASIC 95 Figure A-4 ASIC Die 96 Figure A-6 Reconfigurable SoC . 103 Figure A-7 ChipSat OBC . 106 Figure B-1 Behavioral Code 112 Figure B-2 Structural Code 113 Figure B-3 One Line Per Signal/Named Association 114 Figure B-4 Header Template 115 Figure B-5 Process, Functi

21、on, and Procedure Header . 115 Figure B-6 Inline Comments 115 Figure B-7 Proper Indentation 116 Figure B-8 Confusing _in and _out suffixes 118 Figure B-9 Internal Signals Representing Output Ports . 118 Figure B-10 Correct Use of Variables. 121 Figure B-11 Incorrect Use of Variables 122 Figure B-12

22、A Constant Guiding the Generation of Logic . 123 Figure B-13 Address Width Defined by a Constant 124 Figure B-14 Modular Function Use 125 Figure B-15 Use of Types and Aliases . 126 Figure B-16 Three-state Implementation of 4:1 Multiplexer . 129 Figure B-17 Xilinx LUT-RAM Inference 130 Figure B-18 LU

23、T-ROM Inference . 130 Figure B-19 Virtex Block RAM inference . 131 Figure B-20 Clock Enable Inference 133 Figure B-21 Inference of Xilinx Shift Register LUT (SRL) 134 Figure B-22 Local Asynchronous Reset and TC to process sound, video, and images in various ways; and to understand data from sonar, r

24、adar, and seismological readings. Electrically-Erasable Programmable Read-Only Memory (EEPROM): A memory device whose contents can be electrically programmed by the designer. Additionally, the contents can be electrically erased allowing the device to be reprogrammed. Electro-Static Discharge (ESD):

25、 The term electro-static discharge refers to a charged person, or object, discharging static electricity. Although the current associated with such a static charge is low, the electric potential can be in the millions of volts and can severely damage electronic components. Erasable Programmable Read

26、-Only Memory (EPROM): A memory device whose contents can be electrically programmed by the designer. Additionally, the contents can be erased by exposing the die to ultraviolet light through a quartz window mounted in the top of the components package. Falling-Edge: A transition from a logic 1 to a

27、logic 0. Also known as a negative edge. Field Programmable Gate Array (FPGA): High density PLD containing small logic cells interconnected through a distributed array of programmable switches. This type of architecture produces statistically varying results in performance and functional capacity, bu

28、t offers high register counts. Programmability typically is via volatile SRAM (Static Random Access Memory) or one-time-programmable antifuses. Firmware: The combination of a hardware device and computer instructions and/or computer data that reside as read-only software on the hardware device. Firs

29、t-in first-out (FIFO): Data structure or hardware buffer where items come out in the same order they came in. Flash memory: Non-volatile storage device similar to EEPROM, but where erasing can only be done in blocks or the entire chip. Provided by IHSNot for ResaleNo reproduction or networking permi

30、tted without license from IHS-,-,-NASA-HDBK 8739.23 with change 1 17 of 143 Flip-flop: A digital logic circuit that can be switched back and forth between two states. Floorplanning: The process of identifying structures that should be placed close together on a chip, and allocating space for them. F

31、use: An electrical device that performs the same function as a fuse. Fuses are widely used to permanently program integrated circuits by opening an electrical connection. Gate: In electronic circuitry, a pathway that may be open or closed, depending on the source of the input, the strength of a sign

32、al, or the conductivity of chemicals used in semiconductors. Logic gates are programmed to correspond to related “if-then“ statements. The state of an open or closed gate is analogous to the binary state of a 0 or a 1. The application of this analogy allows computing machinery with millions of gates

33、 to respond conditionally and to perform logical functions. Gate Array: Integrated circuit that is customized by interconnecting an array of logic elements. Customization is performed by the manufacturer and typically involves non-recurring engineering costs and several design iterations. Glue: Gene

34、ric term for any interface logic or protocol that connects two component blocks. Hardware designers call anything used to connect large VLSIs or circuit blocks “glue logic.“ Hardware Description Language (HDL): A kind of language used for the conceptual design of integrated circuits. Examples are VH

35、DL and Verilog. Integrated Circuit (IC): A device in which components such as resistors, capacitors, diodes, and transistors are formed on the surface of a single piece of semiconductor. In-Circuit Reconfigurable (ICR): An SRAM-based or similar component which can be dynamically reprogrammed on-the-

36、fly while remaining resident in the system. In-System Programmable (ISP): An EEPROM-based, flash-based, or similar component which can be reprogrammed while remaining resident on the circuit board. JHDL: A structurally based hardware description language implemented with the Java programming languag

37、e. JHDL is a method of describing (programmatically, in Java) the components and connections in a digital logic circuit. More specifically, JHDL provides object classes used to build up circuit structure. Joint Electronic Device Engineering Council (JEDEC): A council which creates, approves, arbitra

38、tes, and oversees industry standards for electronic devices. In programmable logic, the term JEDEC refers to a textual file containing information used to program a device. The file format is a JEDEC approved standard and is commonly referred to as a JEDEC file. Joint Test Action Group (JTAG): (or “

39、IEEE Standard 1149.1“). A standard specifying how to control and monitor the pins of compliant devices on a printed circuit board. JTAG is a standard interface used for in-system testing and debugging. Logic: One of the three major classes of integrated circuits in most digital electronic systems. T

40、he other two major classes are microprocessors and memory. Logic is used for data manipulation and control functions that require higher speed than a microprocessor can provide. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-NASA-HDBK 8739.23 with c

41、hange 1 18 of 143 Logic Function: A mathematical function that performs a digital operation on digital data and returns a digital value. Logic Gate: The physical implementation of a logic function. Logic Synthesis: A process in which a program is used to optimize the logic used to implement a design

42、. Look-Up Table (LUT): An array or matrix of values that contains data that is searched. An alternative implementation of a CLB; the multiple inputs generate the complex outputs. Macrocell: A macrocell on most modern CPLDs contains a sum-of-products combinatorial logic function and an optional flip-

43、flop. The combinatorial logic function typically supports four to sixteen product terms with wide fan-in. Thus, a macrocell may have many inputs, but the logic function complexity is limited. On the other hand, most FPGA logic blocks have unlimited complexity, but the logic function only has four in

44、puts. Mapping: The process of taking the logic blocks and determining what logic gates and interconnections on the device should be used to implement those blocks. Netlist: A list of names of symbols or parts and their connection points, which are logically connected in each net of a circuit. A file

45、 listing parameters extracted from a circuit schematic. Noise: The miscellaneous rubbish that gets added to a signal on its journey through a circuit. Noise can be caused by capacitive or inductive coupling, or from externally generated interference. Non-volatile: The ability of a memory element to

46、keep its contents when power is removed from the device. Onboard: Contained on the device or on the board. One Time Programmable: This device can be programmed only once; its contents cannot be changed. While typically these devices are fuse or antifuse based, they can also be low-cost EPROM devices

47、. In this case, typically used for production devices, an inexpensive package is used without a window. Partial Reprogrammability: The ability to leave some internal logic in place and change another part of the FPGA logic. Pinout: A diagram that indicates how wires are terminated to pins in a conne

48、ctor; a list that assigns device functions to specific pins. Place and Route: Converts the results of the synthesis process to the format supported and takes the logic blocks and determines what logic gates and interconnections on the device should be used to implement those blocks. Programmable Logic: A logic element whose function is not restricted to a particular function. It may be programmed at different points of the life cycle. At the earliest, it is programmed by the semiconductor vendor (standard cell, gate array), by the designer prior to assembly, or by the user, in circ