SAE AS 6171 11-2016 Techniques for Suspect Counterfeit EEE Parts Detection by Design Recovery Test Methods.pdf

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4、side USA)Fax: 724-776-0790Email: CustomerServicesae.orgSAE WEB ADDRESS: http:/www.sae.orgSAE values your input. To provide feedback on thisTechnical Report, please visithttp:/standards.sae.org/AS6171/11AEROSPACESTANDARDAS6171/11Issued 2016-10Techniques for Suspect/Counterfeit EEE Parts Detection by

5、Design Recovery Test MethodsRATIONALEThis document was created to provide guidelines for the application of Design Recovery and to define the compliance requirements for laboratories using this technique. Additionally, this document is intended to provide guidance for those unfamiliar with Design Re

6、covery and its application to detection of counterfeit electronic parts. This technique can be used for any risk level as needed to support results from other analysis techniques. INTRODUCTIONDesign Recovery is a destructive process used to obtain design information directly from a microcircuit. In

7、the context of counterfeit detection this method could allow for the determination of whether the recovered design information of a microcircuit matches the intended function or physical layout of a known “good” or “control” sample or matches the original design. This method can be applied to detect

8、ing changes in the microcircuit intended function through analysis of the physical layout of the circuit. These changes may be either non-malicious or unintentional, or they may be intentionally malicious (Trojan circuitry), such as a kill switch or to enable unauthorized access to the device or the

9、 product in which the device is used. Examples of physical defects which are indicators of a possible counterfeit device for which design recovery is particularly well suited include: wrong die, missing and/or misaligned contact window, parasitic transistors, cracks and other imperfections in a sili

10、con die or passivation layer or electromigration. However, it must be noted that circuits with the same functional behavior may have different physical design either due to a revised design, newer technology or different implementations of the same functional behavior from different manufacturers an

11、d therefore may not be counterfeit. This procedure requires the availability of either a known authentic sample or information on the design of the device.This document is focused on Design Recovery as it pertains to microcircuits, although it can be related to other electronic products such as disc

12、rete semiconductor devices or electronic devices with embedded microcircuits. The technique is a fundamentally destructive technique that requires decapsulation and removal of the silicon die from its packaging. The procedure outlined in this document assumes the design information is recovered from

13、 a silicon die, a layer at a time by sequential imaging and layer removal, thus recovering the original layout information used to manufacture the microcircuit. This approach ensures all the circuit design information can be captured, if required, so any “hidden” function is not missed. Non-destruct

14、ive techniques are being researched and may be available in the future.Depending on the complexity of the microcircuit under investigation and the required level of analysis required, Design Recovery can be an extremely time consuming and complex process; therefore, it may only be practical for micr

15、ocircuits with a Critical Risk Level. A microcircuit is removed from its packaging and sequentially each circuit layer is imaged and then removed so that the original design can be reconstructed. Potential applications of Design Recovery for counterfeit detection include microcircuit die-level authe

16、ntic sample or design comparison to assess possible design modifications.SAE INTERNATIONAL AS6171/11 Page 2 of 10TABLE OF CONTENTS1. SCOPE 32. REFERENCES 32.1 Applicable Documents 32.1.1 SAE Publications. 32.1.2 Other Publications. 32.2 Terms and Definitions . 32.3 Acronyms 33. EQUIPMENT AND OTHER S

17、UPPLIES 43.1 Sample Preparation Equipment 43.2 Data Capture and Analysis . 43.2.1 Equipment Limitations. 43.3 General Laboratory Supplies 44. TEST SAMPLE . 44.1 Sample Limitations 45. MATERIALS HANDLING, STORAGE, AND SAMPLE PREPARATION 56. DESCRIPTION OF METHODOLOGY 56.1 Introduction . 56.2 Test Pla

18、n . 56.3 Data Collection (Imaging) 67. CONTROLS AND CALIBRATION 77.1 Etching and Polishing 77.2 Data Capture. 78. ANALYSIS AND INTERPRETATION OF DATA. 78.1 Comparison Techniques of Sample Under Investigation Data to Layout Data 78.1.1 Non-Automated Visual Image/Data Inspection. 78.1.2 Automated Layo

19、ut Comparison 78.1.3 Functional Analysis . 89. REPORTING OF RESULTS . 810. QUALIFICATION AND CERTIFICATION . 910.1 Personnel Qualification . 910.1.1 Level 3 - Advanced Interpretation (Typically Device Physicist, Microcircuit Designer, Semiconductor Failure Analyst or Electrical Engineer) 910.1.2 Lev

20、el 2 - Basic Interpretation (Typically Technician, Microcircuit Designer or Electrical Engineer). 910.1.3 Level 1 - Operation (Typically an Operator) 1010.2 Safety 1011. NOTES 1011.1 Revision Indicator 10TABLE 1 DESIGN RECOVERY COMPLEXITY LEVELS 5TABLE 2 COMPARISON OF SAMPLE PREPARATION TECHNIQUES 6

21、TABLE 3 COMPARISON OF IMAGING TECHNIQUES 6TABLE 4 REQUIRED TEST REPORT INFORMATION. 8SAE INTERNATIONAL AS6171/11 Page 3 of 101. SCOPEThis method outlines the requirements, capabilities, and limitations associated with the application of Design Recovery for the detection of counterfeit electronic par

22、ts including: Operator training; Sample preparation; Imaging techniques; Data interpretation; Design/functional matching; Equipment maintenance and; Reporting of data. The method is primarily aimed at analyses performed by circuit delayering and imaging with a scanning electron microscope or optical

23、 microscope; however, many of the concepts are applicable to other microscope and probing techniques to recover design data. The method is not intended for the purpose of manufacturing copies of a device, but rather to compare images or recover the design for determination of authenticity.If AS6171/

24、11 is invoked in the contract, the base document, AS6171 General Requirements shall also apply.2. REFERENCES2.1 Applicable DocumentsThe following publications form a part of this document to the extent specified herein. The latest issue of SAE publications shall apply. The applicable issue of other

25、publications shall be the issue in effect on the date of the purchase order. In theevent of conflict between the text of this document and references cited herein, the text of this document takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a speci

26、fic exemption has been obtained.2.1.1 SAE PublicationsAvailable from SAE International, 400 Commonwealth Drive, Warrendale, PA 15096-0001, Tel: 877-606-7323 (inside USA and Canada) or +1 724-776-4970 (outside USA), www.sae.org.AS6171 Test Methods Standard: General Requirements, Suspect/Counterfeit E

27、lectrical, Electronic, and Electromechanical PartsAS6171/4 Techniques for Suspect/Counterfeit EEE Parts Detection by Delid/Decapsulation Physical Analysis Test Methods2.1.2 Other PublicationsANSI/ESD S20.20 Protection of Electrical and Electronic Parts, Assemblies and EquipmentANSI/ISO/IEC 17025:200

28、0 General Requirements for the Competence of Testing and Calibration LaboratoriesIDEA-STD-1010 Acceptability of Electronic Components Distributed in the Open MarketIPC/JEDEC J-STD-020 Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount DevicesIPC/JEDEC J-STD-033 Hand

29、ling, Packing, Shipping and Use of Moisture/Reflow Sensitive Surface Mount DevicesJESD-625 Requirements for Handling Electrostatic Discharge Sensitive (ESD) Devices2.2 Terms and DefinitionsAll terms that require definition are defined in the paragraph in which they are first used.2.3 AcronymsSee 2.3

30、 of AS6171 General Requirements.SAE INTERNATIONAL AS6171/11 Page 4 of 103. EQUIPMENT AND OTHER SUPPLIESDesign Recovery is a multistep process that requires a range of capabilities and tools; the specific equipment is dependent on the particular microcircuits under investigation. No one system is cur

31、rently available, but a range of tools for sample preparation, data capture and analysis are required.3.1 Sample Preparation EquipmentFor the purpose of removing circuit layers, one layer at a time, equipment to enable at least one of the following techniquesshall be used - wet chemical etching, dry

32、 Reactive Ion Etching (RIE), Chemical Mechanical Polishing (CMP) and Focused Ion Beam (FIB) milling. Standard sample preparation tools and chemicals including microscopes and ultrasonic cleaning baths, as selected by the lab, shall be available for sample preparation. The use of chemicals and gases

33、shall require the correct safety equipment such as fume hoods, protective clothing, handling tools as required by local laws and manufacturers guidance.3.2 Data Capture and AnalysisMicroscopy of the circuit layer under investigation shall be used to capture the circuits design layout. The use of a s

34、canning electron microscope (SEM) with automated data capture is recommended; however, depending on the information required other techniques may be utilized, such as optical microscopy, scanning probe techniques and X-ray techniques. Software for image processing and conversion into design data is

35、highly recommended. Software is available that enables image capture, processing, and analysis, stage motion control, image distortion reduction, and conversion to CAD (Computer Aided Design) layout format. Electronic Design Automation (EDA) software for simulation and design analysis may also be he

36、lpful to analyze the circuit function completely. The selection of specific software package(s) will depend on the type andmanufacturer of the microscope or cameras employed for imaging as well as the level of detail required by the analysis.3.2.1 Equipment LimitationsThe imaging technique used will

37、 have resolution limits, sample size limitations or the need for conducting samples. For example, standard optical microscopy is limited to around 1 micron resolution, which limits its use to older technology microcircuits, whereas, with nanometer resolution, electron-beam microscopes have the capab

38、ility to image modern, complex microcircuits. Also the time to collect and analyze data can vary significantly depending on the circuit complexity and imaging technique and data processing techniques used.3.3 General Laboratory Supplies Supplies required for decapsulation or delidding shall be avail

39、able as specified in AS6171/4, Section 4 (Apparatus andEquipment). Additional supplies required for the proper handling, cleaning, and preparation of samples, including delayering,and for the maintenance of equipment shall include chemicals and gases and appropriate safety protection. The specific s

40、upplies required will vary depending on the techniques employed, as specified in Section 6.4. TEST SAMPLEThe samples tested will be variable although they will generally consist of a single microcircuit device, and best practices for the analysis method chosen shall be followed. Additional samples m

41、ay be required in order to determine whether subtle differences in features or dimensions were caused by normal manufacturing variations.4.1 Sample LimitationsA known authentic sample or design shall be available to enable comparison of the recovered design in order to identify differences that woul

42、d indicate a suspect counterfeit device. The requisite sample or design information should be obtained from the original component manufacturer if possible. The technology of the Device Under Test (DUT) and the test requirements will dictate the techniques that are appropriate for use; for example,

43、the methods required to decapsulate and physically remove circuit layers will be dependent on the DUTs method of manufacture and the materials used, minimum feature size and overall complexity. RIE or wet chemical etching may be sufficient for one technology but inadequate for another. The process i

44、s destructive and therefore can only be used to demonstrate that a sample taken from a batch is suspected of being a counterfeit.SAE INTERNATIONAL AS6171/11 Page 5 of 105. MATERIALS HANDLING, STORAGE, AND SAMPLE PREPARATIONESD sensitive items shall be handled from receipt to delivery in accordance w

45、ith ANSI/ESD S20.20 or JESD-625. Moisture sensitive items shall be handled from receipt through delivery in accordance with the requirements of IPC/JEDEC J-STD-20 and J-STD-033. Refer to the requirements in 3.9.5 of AS6171 General Requirements NOTE: IDEA-STD-1010 Sections 7.1 and 7.3 provide worksta

46、tion guidelines.6. DESCRIPTION OF METHODOLOGYThe microcircuit die shall be exposed from its packaging per AS6171/4. Subsequently, the ability to cleanly remove circuit layers, one layer at a time, is essential to ensure accurate data capture. A series of techniques for delayering may be required dep

47、ending on the circuit technology and complexity, including wet chemical etching, dry RIE, CMP and FIB milling. Standard sample preparation tools and chemicals including microscopes and ultrasonic cleaning baths, as selected by the lab, shall be available for sample preparation. The use of chemicals

48、and gases shall require the correct safety equipment such as fume hoods, protective clothing, handling tools as required by local laws and manufacturers guidance.6.1 IntroductionElectrical testing allows a microcircuit to be analyzed for known functionality but testing for all possible functions bec

49、omesa very complex task. One method of fully understanding a microcircuits function is to recover the original design data that was used to manufacture it. Microcircuits are complex three dimensional layered structures with metal connectivity, dielectricand semiconductor layers. A microcircuit die is exposed (reference AS6171/4) and each circuit layer is removed one layer at a time and imaged so that the original mask data used to man