TIA-422-B-1994 Electrical Characteristics of Balanced Voltage Digital Interface Circuits《平衡电压数字接口电路的电气特性》.pdf

1、 TIA/EIA-422-B-1994 APPROVED: APRIL 13, 1994 REAFFIRMED: JANUARY 27, 2000 REAFFIRMED: SEPTEMBER 16, 2005 REAFFIRMED: JULY 29, 2014 TIA-422-B (Revision of EIA-422-A) May 1994Electrical Characteristics of Balanced Voltage Digital Interface Circuits NOTICE TIA Engineering Standards and Publications are

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20、IMITATIONS. FOREWORD (This foreword is not part of this Standard) This Standard, from Standards Proposal No. 1849, was formulated under the cognizance of TIA Subcommittee TR-30.2 on Data Transmission Interfaces. This Standard specifies generators and receivers capable of operating at data signaling

21、rates up to 10 Mbitls. No technical changes have been incorporated into TIAIEIA-422-B which will create compatibility problems with equipment conforming to previous versions of TIAIEIA-422. This Standard provides an additional termination option not specified in EIA-422-A. This option is an RC termi

22、nation, and is optimal for use on low speed control lines where power dissipation is a major concern. Annex A of this Standard is informative and provides guidelines for application. Annex B of this Standard is also informative and provides information on compatibility with other interface standards

23、, and references to this Standard. Neither Annex is considered part of this Standard. BLANK PAGE TINEIA-422-B ELECTRICAL CHARACTERISTICS OF BALANCED VOLTAGE DIGITAL INTERFACE CIRCUITS CONTENTS Page SCOPE 1 . DEFINITIONS 2 APPLICABILITY . 2 ELECTRICAL CHARACTERISTICS 5 Generator Characteristics 5 Gen

24、erator Output Impedance 6 Open Circuit Measurements . 7 Test Termination Measurements 7 Short-circuit Measurement 8 Power-off Measurement . 8 Output Signal Waveform 8 . . Load Charactenstcs 10 Input Current-Voltage Measurements . 10 Input Sensitivity Measurements . 10 Input Balance Measurements . 13

25、 Cable Termination . 13 Multiple Receiver Operation 14 Failsafe Operation 15 Total Load Limit 16 Interconnecting Cable Characteristics 16 ENVIRONMENTAL CONSTRAINTS . 17 CIRCUIT PROTECTION 17 OPTIONAL GROUNDING ARRANGEMENTS . 18 Signal Common 18 Configuration “A“ . 19 Configuration “B“ 19 iii Content

26、s Page 7.2 Shield Ground 19 ANNEX A (informative) 20 A . 1 Interconnecting Cable and Termination 20 A.l.l Cable Length with Resistive Termination (Option 1) 20 A.1.2 Cable Termination 22 A.2 Codirectional and Contradirectional Timing Information . 23 ANNEX B (informative) . 24 B . 1 Compatibility wi

27、th Other Interface Standards . 24 8.2 Related TlAlEIA Standards 25 1 SCOPE This Standard specifies the electrical characteristics of the balanced voltage digital interface circuit, normally implemented in integrated circuit technology, that may be employed when specified for the interchange of seria

28、l binary signals between Data Terminal Equipment (DTE) and Data Circuit-Terminating Equipment (DCE) or in any point-to-point interconnection of serial binary signals between digital equipment. This Standard is compatible with ITU-T (Formally CCITT) Recommendation v.11. The interface circuit includes

29、 a generator connected by a balanced interconnecting cable to a load consisting of a receiver or receivers and a termination. The electrical characteristics of the circuit are specified in terms of required voltage, current, and resistance values obtained from direct measurements of the generator an

30、d receiver components at the interface points. The logic function of the generator and the receiver is not defined by this Standard, as it is application dependent. The receiver specification for the balanced interface is identical to that specified for the unbalanced interface circuit in TIA/EIA-42

31、3-B. Minimum performance requirements for the interconnecting cable are furnished. Guidance is given in Annex A.l with respect to limitations on data signal rate imposed by the parameters of the cable length, balance, and termination, for individual installations. The parameter values specified for

32、the balanced generator and load components of the interface are designed such that balanced interface circuits may be used within the same interconnection as unbalanced interface circuits specified by TINEiA-423-B. For example, the balanced circuits may be used for data and timing while the unbalanc

33、ed circuits may be used for low speed control functions. It is intended that this Standard will be referenced by other standards that specify the complete DTEIDCE interface (e.g., connector, pin assignments, function) for applications where the electrical characteristics of a balanced voltage digita

34、l circuit are required. This Standard does not specify other characteristics of the DTVDCE interface (such as signal quality and timing, etc.) essential for proper operation across the interface. When this Standard is referenced by other standards or specifications, it should be noted that certain o

35、ptions are available. The preparer of those standards and specifications must determine and specify those optional features that are required for that application. 2 DEFINITIONS In this Standard, the term: data signaling rate, expressed in the units bit such as, in biphase encoded systems where the

36、data signaling rate is twice the data transfer rate. star () represents the opposite input condition for a parameter. For example, the symbol Q represents the receiver output state for one input condition, while Q represents the output state for the opposite input state. 3 APPLICABILITY The provisio

37、ns of this Standard may be applied to the circuits employed at the interface between equipments where information being conveyed is in the form of binary signals at the dc baseband level. This Standard shall be referenced by the specifications and specific interface standards applying these electric

38、al characteristics. Typical points of applicability for this Standard are depicted in figure 1. Legend: DTE = Data Terminal Equipment = Interface Generator DCE = Data Circuit-Terminating Equipment , = Interface Receiver + = Telecommunications Channel - = Balanced Interface Ciait Figure 1 - Applicati

39、ons of balanced voltage digital interface circuit The balanced voltage digital interface circuit will normally be utilized on data and timing, or control circuits where the data signaling rate is up to 10 MbiUs. Balanced voltage digital interface devices meeting the electrical characteristics of thi

40、s Standard need not operate over the entire data signaling rate range specified. They may be designed to operate over a narrower ranges to satisfy more economically specific applications, particularly at the lower data signaling rates. While the balanced interface is intended for use at the higher d

41、ata signaling rates, it may (in preference to the unbalanced interface circuit) generally be required where any of the following conditions prevail: a. The interconnecting cable is too long for effective unbalanced operation. b. The interconnecting cable is exposed to extraneous noise sources that m

42、ay cause an unwanted voltage in excess of *1V measured differentially between the signal conductor and circuit common at the load end of the cable with a 50 R resistor substituted for the generator. c. It is necessary to minimize interference with other signals. d. Inversion of the signals may be re

43、quired; e.g., plus MARK to minus MARK may be obtained by inverting the cable pair. While a restriction of maximum cable length in not specified, guidelines are given with respect to conservative operating distances as a function of data signaling rate (see Annex A). In general, these conservative va

44、lues may be greatly exceeded where the installation is engineered to ensure that noise and ground potential values are held within specified limits. 4 ELECTRICAL CHARACTERISTICS The balanced voltage digital interface circuit is shown in figure 2. The circuit consists of three parts: the generator (G

45、), the balanced interconnecting cable. and the load. The load is composed of one or more receivers (R) and a cable termination (21). The electrical characteristics of the generator and receiver are specified in terms ofdirect electrical measurements while the interconnecting cable is described in te

46、rms of its electrical and physical characteristics. BALANCED INTERFACE - GENERATO LOAD i Cable : Termi- : i-4 RECEIVER, + : . Legend : G = Generator A,B = Generator Interface Points R = Receiver A,B1 = Receiver Interface Points Zt = Termination C = Generator Circuit Common Vg = Common Potential Cq =

47、 Receiver Circuit Common Difference Note: The physical connections of multiple receivers is not defined. See 4.2.5 for recommendations. Termination should be located only at the extreme end of the cable. Figure 2 - Balanced voltage digital interface circuit 4.1 Generator Characteristics The generato

48、r slectrical characteristics are specified in accordance with the measurements illustrated in figures 3 to 8 and described in Paragraphs 4.1.1 through 4.1.6. The generator circuit meeting these requirements results in a low impedance balanced voltage source that will produce a differentia! voltage a

49、pplied to the interconnecting cable in the range of 2 V to 10 V. The signaling sense of the voltages appearing across the interconnecting cable are defined in figure 3 as follows: a. The A terminal of the generator shall be negative with respect to the B terminal for a binary 1 (MARK or OFF) state. b. The A terminal of- the generator shall be positive with respect to the B terminal for a binary 0 (SPACE or ON) state. The logic function of the generator and the receiver is beyond the scope of this Standard, and therefore is not defined. MARK SPACE MARK 1 0 1 OFF ON OFF Vob VOH Voa VOL