IEC 60424-5-2009 Ferrite cores - Guide on the limits of surface irregularities - Part 5 Planar-cores《铁氧体磁芯.表面缺陷的限值指南.第5部分 平面磁芯》.pdf

1、 IEC 60424-5 Edition 1.0 2009-02 INTERNATIONAL STANDARD NORME INTERNATIONALE Ferrite cores Guide on the limits of surface irregularities Part 5: Planar-cores Noyaux de ferrite Guide relatif aux limites des irrgularits de surface Partie 5: Noyaux planaires IEC 60424-5:2009 THIS PUBLICATION IS COPYRIG

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16、l: csciec.ch Tl.: +41 22 919 02 11 Fax: +41 22 919 03 00 IEC 60424-5 Edition 1.0 2009-02 INTERNATIONAL STANDARD NORME INTERNATIONALE Ferrite cores Guide on the limits of surface irregularities Part 5: Planar-cores Noyaux de ferrite Guide relatif aux limites des irrgularits de surface Partie 5: Noyau

17、x planaires INTERNATIONAL ELECTROTECHNICAL COMMISSION COMMISSION ELECTROTECHNIQUE INTERNATIONALE N ICS 29.100.10 PRICE CODE CODE PRIX ISBN 2-8318-1050-5 Registered trademark of the International Electrotechnical Commission Marque dpose de la Commission Electrotechnique Internationale 2 60424-5 IEC:2

18、009 CONTENTS FOREWORD.3 1 Scope.5 2 Normative references .5 3 Limits of surface irregularities.6 3.1 Chips and ragged edges6 3.1.1 Chips and ragged edges on the mating surfaces (see Figures 1, 2 and 3)6 3.1.2 Chips and ragged edges on other surfaces7 3.2 Cracks.10 3.3 Flash.10 3.4 Pull-out .10 Figur

19、e 1 Chip location for planar EL-core.6 Figure 2 Chip location for low profile E-core.6 Figure 3 Chip location for low profile ER-core 6 Figure 4 Cracks and pull-out location for planar EL-core10 Figure 5 Cracks and pull-out location for low profile E-core11 Figure 6 Cracks and pull-out location for

20、low profile ER-core .11 Figure 7 Reference dimensions for EL-core .11 Figure 8 Reference dimensions for E-core .12 Figure 9 Reference dimensions for ER-core.13 Table 1 Allowable areas of chips in mm 2for planar EL-core.7 Table 2 Allowable areas of chips in mm 2for low profile E-core 8 Table 3 Allowa

21、ble areas of chips in mm 2for low profile ER-core8 Table 4 Area and length reference for visual inspection .9 Table 5 Limits of cracks for planar EL-core 12 Table 6 Limits of cracks for low profile E-core13 Table 7 Limits of cracks for low profile ER-core .14 60424-5 IEC:2009 3 INTERNATIONAL ELECTRO

22、TECHNICAL COMMISSION _ FERRITE CORES GUIDE ON THE LIMITS OF SURFACE IRREGULARITIES Part 5: Planar-cores FOREWORD 1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising all national electrotechnical committees (IEC National Committees). The o

23、bject of the IEC is to promote international co-operation on all questions concerning standardization in the electrical and electronic fields. To this end and in addition to other activities, IEC publishes International Standards, Technical Specifications, Technical Reports, Publicly Available Speci

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31、ation, use of, or reliance upon, this IEC Publication or any other IEC Publications. 8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is indispensable for the correct application of this publication. 9) Attention is drawn to the possibil

32、ity that some of the elements of this IEC Publication may be the subject of patent rights. IEC shall not be held responsible for identifying any or all such patent rights. International Standard IEC 60424-5 has been prepared by IEC technical committee 51: Magnetic components and ferrite materials. T

33、his bilingual version, published in 2009-07, corresponds to the English version. The text of this standard is based on the following documents: FDIS Report on voting 51/947/FDIS 51/950/RVD Full information on the voting for the approval of this standard can be found in the report on voting indicated

34、 in the above table. The French version of this standard has not been voted upon. This publication has been drafted in accordance with the ISO/IEC Directives, Part 2. 4 60424-5 IEC:2009 A list of all parts of the IEC 60424 series, under the general title Ferrite cores Guide on the limits of surface

35、irregularities, can be found on the IEC website. The committee has decided that the contents of this publication will remain unchanged until the maintenance result date indicated on the IEC web site under “http:/webstore.iec.ch“ in the data related to the specific publication. At this date, the publ

36、ication will be reconfirmed, withdrawn, replaced by a revised edition, or amended. 60424-5 IEC:2009 5 FERRITE CORES GUIDE ON THE LIMITS OF SURFACE IRREGULARITIES Part 5: Planar-cores 1 Scope This part of IEC 60424 gives guidance on allowable limits of surface irregularities applicable to planar-core

37、s in accordance with the relevant generic specification defined in IEC 60424-1. The relations between the main dimensions of planar E-, ER- and EL-cores differ from those of standard cores. For example, the width of planar cores is larger while the total height is much smaller. Also the thickness of

38、 the legs is in most cases smaller than compared to standard cores. Therefore the concept of fixed reference dimensions to determine the length of crack limits yield crack lengths which are not acceptable for this type of core. This part of IEC 60424 follows another concept which relates the crack l

39、ength to dimensions of the surface on which the crack occurs. Also the concept to determine the maximum area of chips based on the total mating surface fails in the case of planar cores. The outer legs of planar cores are much thinner than those of standard cores which makes overlapping and gluing m

40、uch more difficult. A single chip of maximum size on the outer leg may risk the functionality of the core set. Therefore this standard uses as a reference the mating surface on which the chip occurs. Windings of planar cores are often PCBs which are glued to the inner surfaces of the planar core. Fo

41、r this reason the inner surfaces of the planar cores need to have a better quality than the inner surfaces of standard cores. This was taken into account by reducing the maximum allowable area of pull outs in the inner surfaces. This standard is considered as a sectional specification useful in the

42、negotiation between ferrite core manufacturers and users about surface irregularities. 2 Normative references The following referenced documents are indispensable for the application of this document. For dated references, only the edition cited applies. For undated references, the latest edition of

43、 the referenced document (including any amendments) applies. IEC 60424-1, Ferrite cores Guide on the limits of surface irregularities Part 1: General specification IEC 62317-9, Ferrite cores Dimensions Part 9: Planar cores 6 60424-5 IEC:2009 3 Limits of surface irregularities 3.1 Chips and ragged ed

44、ges 3.1.1 Chips and ragged edges on the mating surfaces (see Figures 1, 2 and 3) C1 Mating surfaces Ragged edges C1 IEC 360/09 Figure 1 Chip location for planar EL-core C2 Mating surfaces Ragged edges C1 C1 IEC 361/09 Figure 2 Chip location for low profile E-core Wire slot area C2 Mating surfaces Ra

45、gged edges C1 C1 IEC 362/09 Figure 3 Chip location for low profile ER-core Areas of the chips located on the mating surfaces (C1 and C1 irregularities in Figures 1, 2 and 3) shall not exceed the following limits: the cumulative area of the chips shall be less than 4 % of the relevant mating surface.

46、 The mating surface of each outer leg and centre post is considered separately; the allowable areas are rounded to the figures in Table 4 (Area and length reference for visual inspection) and the minimum allowable area is taken as 0,5 mm 2to be distinguishable to the naked eye; 60424-5 IEC:2009 7 th

47、e total area of all chips on all mating surfaces shall not exceed the value given for “overall chipping on the mating surface” in Tables 1, 2 or 3; the total length of the ragged edges shall be less than 25 % of the perimeter of the relevant mating surface. 3.1.2 Chips and ragged edges on other surf

48、aces the allowable chipping areas are doubled as compared to the limits for the whole mating surfaces (see Table 1 for planar EL-cores, Table 2 for low profile E-cores, Table 3 for low profile ER-cores); the total length of the ragged edges shall be less than 25 % of the perimeter of the smaller adj

49、oining surface; chips and ragged edges are not acceptable on the ridge of the clamping recess area; chips and ragged edges are not acceptable on the inner edges of wire slot area (C2 irregularity in Figures 2 and 3). The core sizes given in Tables 1, 2 and 3 correspond to the cores defined in IEC 62317-9, and area and length reference for visual insp