IEC 62374-1-2010 Semiconductor devices - Part 1 Time-dependent dielectric breakdown (TDDB) test for inter-metal layers《半导体器件.第1部分 金属层之间的时间相关的介质击穿(TDDB)试验》.pdf

1、 IEC 62374-1 Edition 1.0 2010-09 INTERNATIONAL STANDARD NORME INTERNATIONALE Semiconductor devices Part 1: Time-dependent dielectric breakdown (TDDB) test for inter-metal layers Dispositifs semiconducteurs Partie 1: Essai de rupture dilectrique en fonction du temps (TDDB) pour les couches intermtall

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16、tions, visitez le FAQ du Service clients ou contactez-nous: Email: csciec.ch Tl.: +41 22 919 02 11 Fax: +41 22 919 03 00 IEC 62374-1 Edition 1.0 2010-09 INTERNATIONAL STANDARD NORME INTERNATIONALE Semiconductor devices Part 1: Time-dependent dielectric breakdown (TDDB) test for inter-metal layers Di

17、spositifs semiconducteurs Partie 1: Essai de rupture dilectrique en fonction du temps (TDDB) pour les couches intermtalliques INTERNATIONAL ELECTROTECHNICAL COMMISSION COMMISSION ELECTROTECHNIQUE INTERNATIONALE P ICS 31.080 PRICE CODE CODE PRIX ISBN 978-2-88912-178-6 Registered trademark of the Inte

18、rnational Electrotechnical Commission Marque dpose de la Commission Electrotechnique Internationale colour inside 2 62374-1 IEC:2010 CONTENTS FOREWORD.3 1 Scope.5 2 Terms and definitions .5 3 Test equipment.6 4 Test samples6 4.1 General .6 4.2 Test structure6 5 Procedures.8 5.1 General .8 5.2 Pre-te

19、st .8 5.3 Test conditions8 5.3.1 General .8 5.3.2 Electric field 8 5.3.3 Temperature9 5.4 Failure criterion .9 6 Lifetime estimation .10 6.1 General .10 6.2 Acceleration model10 6.3 Formula of E model .10 6.4 A procedure for lifetime estimation 10 7 Lifetime dependence on inter-metal layer area .13

20、8 Summary13 Annex A (informative) Engineering supplementation for lifetime estimation 14 Bibliography16 Figure 1 Schematic image of test structure (comb and serpent pattern) .7 Figure 2 Schematic image of test structure (comb and comb pattern) 7 Figure 3 Cross-sectional image of test structure for l

21、ine to stacked line including via.8 Figure 4 Cross-sectional image of test structure for stacked line to stacked line including via .8 Figure 5 Test flow diagram of constant voltage stress method .9 Figure 6 Weibull distribution plot11 Figure 7 Procedure to estimate the acceleration factor due to th

22、e electric field dependence12 Figure 8 Procedure to estimate the activation energy using an Arrhenius plot12 62374-1 IEC:2010 3 INTERNATIONAL ELECTROTECHNICAL COMMISSION _ SEMICONDUCTOR DEVICES Part 1: Time-dependent dielectric breakdown (TDDB) test for inter-metal layers FOREWORD 1) The Internation

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33、nts of this IEC Publication may be the subject of patent rights. IEC shall not be held responsible for identifying any or all such patent rights. International Standard IEC 62374-1 has been prepared by IEC technical committee 47: Semiconductor devices. The text of this standard is based on the follo

34、wing documents: FDIS Report on voting 47/2063/FDIS 47/2077/RVD Full information on the voting for the approval of this standard can be found in the report on voting indicated in the above table. This publication has been drafted in accordance with the ISO/IEC Directives, Part 2. A list of all the pa

35、rts in the IEC 62374 series, under the general title Semiconductor devices, can be found on the IEC website. 4 62374-1 IEC:2010 The committee has decided that the contents of this publication will remain unchanged until the stability date indicated on the IEC web site under “http:/webstore.iec.ch“ i

36、n the data related to the specific publication. At this date, the publication will be reconfirmed, withdrawn, replaced by a revised edition, or amended. IMPORTANT The colour inside logo on the cover page of this publication indicates that it contains colours which are considered to be useful for the

37、 correct understanding of its contents. Users should therefore print this document using a colour printer. 62374-1 IEC:2010 5 SEMICONDUCTOR DEVICES Part 1: Time-dependent dielectric breakdown (TDDB) test for inter-metal layers 1 Scope This part of IEC 62374 describes a test method, test structure an

38、d lifetime estimation method of the time-dependent dielectric breakdown (TDDB) test for inter-metal layers applied in semiconductor devices. 2 Terms and definitions For the purposes of this document, the following terms and definitions apply. 2.1 leakage current of inter-metal layer I leakcurrent th

39、rough the dielectric layer when a use voltage is applied 2.2 initial leakage current of inter-metal layer I leak-0leakage current of inter-metal layer before a stress voltage is applied 2.3 compliance current I comp maximum current of the voltage-forcing equipment NOTE A compliance limit can be spec

40、ified for a particular test. 2.4 measured leakage current of inter-metal layer I meas measured current in constant voltage stress (CVS) test 2.5 breakdown time t bdsummation of time during which stress voltage is applied to inter-metal layer until failure NOTE In CVS test, applied stress voltage is

41、interrupted by measuring and assessing repeatedly (see Figure 5). 2.6 dielectric layer thickness t d physical thickness of dielectric layer which is pitched between metal lines 2.7 stress voltage V stressvoltage applied during CVS test 6 62374-1 IEC:2010 2.8 use voltage V use voltage applied during

42、pre-test and used for lifetime estimation NOTE This voltage is usually power supply voltage. 2.9 metal electrode length L total length of metal electrode which is pitching the dielectric layer 2.10 electric field for inter-metal layer E imvoltage across a dielectric layer divided by its horizontal w

43、idth between metal lines NOTE The dielectric layer width should be determined by a consistent documented method by the physical measurement method with SEM, TEM or other. The method or a reference to a documented standard which describes the method should be included in the data report. 3 Test equip

44、ment This TDDB test can be applied by both the package level test and the wafer level test. A high temperature oven is used for the package level test. In the case of the wafer level test, a wafer probe with a hot plate or hot chuck is necessary. Additionally the instruments need to have sufficient

45、resolution to detect changes of leakage current under high temperature condition. NOTE Package level test is test on test structures assembled in package. 4 Test samples 4.1 General Test samples for TDDB test for inter-metal layer shall have the following test structure. 4.2 Test structure An approp

46、riate test structure for this test is an interdigitated one as shown in Figure 1, consisting of comb and serpent patterns, which are connected to the voltage source lines. There is an alternative structure, that is the interdigitated comb and comb structure shown in Figure 2. Test structure leads sh

47、all be designed to prevent unexpected failures outside the test structure during the TDDB test. Patterns with vias (Figures 3 and 4) need to be considered because the failure mechanism might be different from a line-to-line pattern without via. Unless otherwise specified comb and serpent pattern are

48、 be recommended. The minimum line-to-line spacing is the most severe condition for this mechanism. Therefore, the minimum dimension allowed by the layout rule shall be evaluated. The total length of the metal line is recommended to be in the range from 0,01 m to 1 m. For the accurate lifetime estima

49、tion, it is recommended that at least three device conditions of area or length be used, so proper scaling can be achieved. Unless otherwise specified the above-mentioned conditions shall be used for test structure parameters. 62374-1 IEC:2010 7 Width of dielectric layer Metal line (serpent pattern) Metal line (comb pattern) Dielectric layer between metal lines V V GND Metal line (comb pattern) IEC 2106