IEC 60191-6-19-2010 Mechanical standardization of semiconductor devices - Part 6-19 Measurement methods of package warpage at elevated temperature and the maxim.pdf

1、 IEC 60191-6-19 Edition 1.0 2010-02 INTERNATIONAL STANDARD NORME INTERNATIONALE Mechanical standardization of semiconductor devices Part 6-19: Measurement methods of the package warpage at elevated temperature and the maximum permissible warpage Normalisation mcanique des dispositifs semiconducteurs

2、 Partie 6-19: Mthodes de mesure du gauchissement des botiers temprature leve et du gauchissement maximum admissible IEC 60191-6-19:2010 colour inside THIS PUBLICATION IS COPYRIGHT PROTECTED Copyright 2010 IEC, Geneva, Switzerland All rights reserved. Unless otherwise specified, no part of this publi

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17、TERNATIONALE Mechanical standardization of semiconductor devices Part 6-19: Measurement methods of the package warpage at elevated temperature and the maximum permissible warpage Normalisation mcanique des dispositifs semiconducteurs Partie 6-19: Mthodes de mesure du gauchissement des botiers tempra

18、ture leve et du gauchissement maximum admissible INTERNATIONAL ELECTROTECHNICAL COMMISSION COMMISSION ELECTROTECHNIQUE INTERNATIONALE M ICS 31.080.01 PRICE CODE CODE PRIX ISBN 2-8318-1078-9 Registered trademark of the International Electrotechnical Commission Marque dpose de la Commission Electrotec

19、hnique Internationale colour inside 2 60191-6-19 IEC:2010 CONTENTS FOREWORD.3 1 Scope.5 2 Normative references .5 3 Terms and definitions .5 4 Sample.9 4.1 Sample size 9 4.2 Solder ball removal .9 4.3 Pretreatment conditions.9 4.4 Maximum time after pretreatment until measurement.9 4.5 Repetition of

20、 the reflow cycles for the sample9 5 Measurement .9 5.1 General description .9 5.2 Temperature profile and the temperatures for measurements 9 5.3 Measurement method10 5.3.1 Shadow moir method .10 5.3.2 Laser reflection method .10 5.3.3 Data analysis (Data table, Diagonal scan graph, 3D plot graph).

21、11 6 Maximum permissible package warpage at elevated temperature.11 7 Recommended datasheet for the package warpage11 7.1 Measurement temperatures for data sheet 11 7.2 Datasheet11 7.3 Example of datasheets 12 Figure 1 Measuring area of BGA and FBGA in full grid layout 6 Figure 2 Measuring area of B

22、GA and FBGA perimeter layout with 4 rows and 4 columns6 Figure 3 Measuring area of FLGA perimeter layout with 4 rows and 4 columns 7 Figure 4 Calculation of the sign of package warpage .8 Figure 5 Package warpage 8 Figure 6 Thermocouple placement .10 Figure 7 Temperature dependency of the package wa

23、rpage 12 Figure 8 Recommended datasheet.13 Table 1 Maximum permissible package warpages for BGA and FBGA11 Table 2 Maximum permissible package warpages for FLGA.11 60191-6-19 IEC:2010 3 INTERNATIONAL ELECTROTECHNICAL COMMISSION _ MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES Part 6-19: Measure

24、ment methods of the package warpage at elevated temperature and the maximum permissible warpage FOREWORD 1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising all national electrotechnical committees (IEC National Committees). The object of

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33、er direct or indirect, or for costs (including legal fees) and expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC Publications. 8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is ind

34、ispensable for the correct application of this publication. 9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of patent rights. IEC shall not be held responsible for identifying any or all such patent rights. International Standard IEC 6019

35、1-6-19 has been prepared by subcommittee 47D: Mechanical standardization for semiconductor devices, of IEC technical committee 47: Semiconductor devices. This standard cancels and replaces IEC/PAS 60191-6-19 published in 2008. This first edition constitutes a technical revision. The text of this sta

36、ndard is based on the following documents: FDIS Report on voting 47D/757/FDIS 47D/764/RVD Full information on the voting for the approval of this standard can be found in the report on voting indicated in the above table. 4 60191-6-19 IEC:2010 This publication has been drafted in accordance with the

37、 ISO/IEC Directives, Part 2. A list of all the parts in the IEC 60191 series, under the general title Mechanical standardization of semiconductor devices, can be found on the IEC website. The committee has decided that the contents of this publication will remain unchanged until the stability date i

38、ndicated on the IEC web site under “http:/webstore.iec.ch“ in the data related to the specific publication. At this date, the publication will be reconfirmed, withdrawn, replaced by a revised edition, or amended. IMPORTANT The colour inside logo on the cover page of this publication indicates that i

39、t contains colours which are considered to be useful for the correct understanding of its contents. Users should therefore print this document using a colour printer. 60191-6-19 IEC:2010 5 MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES Part 6-19: Measurement methods of the package warpage at el

40、evated temperature and the maximum permissible warpage 1 Scope This part of IEC 60191 specifies measurement methods of the package warpage at elevated temperature and the maximum permissible warpages for Ball Grid Array(BGA), Fine-pitch Ball Grid Array (FBGA), and Fine-pitch Land Grid Array (FLGA).

41、2 Normative references The following referenced documents are indispensable for the application of this document. For dated references, only the edition cited applies. For undated references, the latest edition of the referenced document applies. IEC 60191-6-2, Mechanical standardization of semicond

42、uctor devices Part 6-2: General rules for the preparation of outline drawings of surface mounted semiconductor device packages Design guide for 1,50 mm, 1,27 mm and 1,00 mm pitch ball and column terminal packages IEC 60191-6-5, Mechanical standardization of semiconductor devices Part 6-5: General ru

43、les for the preparation of outline drawings of surface mounted semiconductor device packages Design guide for fine-pitch ball grid array (FBGA) 1IEC 60749-20, Semiconductor devices Mechanical and climatic test methods Part 20: Resistance of plastic-encapsulated SMDs to the combined effect of moistur

44、e and soldering heat 3 Terms and definitions For the purposes of this document, the following terms and definitions apply. 3.1 measuring area area for measurement of package warpage, composed of either terminal-existing area bordered by the lines connecting the centres of the outermost neighbouring

45、solder balls for the packages with the standoff height more than 0,1 mm, including BGA and FBGA NOTE Examples of measurement area is shown in Figure 1 and Figure 2. If there are balls at the package centre, their area is also considered as a part of measuring areas. substrate surface except certain

46、edge margin for the packages with the standoff height of 0,1 mm or less, including FLGA NOTE Examples of measurement area is shown in Figure 3. The width of this margin L depends on the capability of each measuring instrument (L = 0,2 mm recommended). 1hereinafter referred as “FBGA design guide“. 6

47、60191-6-19 IEC:2010 (M E 1) e e e (M D 1) e M DA B C 123 M E IEC 108/10 NOTE 1) The hatched area indicates the measuring area. 2) Symbols in this figure are specified to FBGA design guide (IEC 60191-6-5). Figure 1 Measuring area of BGA and FBGA in full grid layout (M E 1) e e M DA B C 1 2 3 M E (M E

48、 7) e e (M D 7) e (M D 1) e IEC 109/10 NOTE Symbols in this figure are specified to FBGA design guide (IEC 60191-6-5). Figure 2 Measuring area of BGA and FBGA perimeter layout with 4 rows and 4 columns 60191-6-19 IEC:2010 7 L IEC 110/10 NOTE The edge margin L indicates the exempt area from measureme

49、nt to avoid measurement noise depending on the instrument capability. Recommended edge margin L = 0,2 mm. Figure 3 Measuring area of FLGA perimeter layout with 4 rows and 4 columns 3.2 convex warpage arched top surface (not interconnect side) of package being mounted on PWB, wherein the sign of the convex warpage is defined as plus 3.3 con