IEEE 1149 10-2017 en High-Speed Test Access Port and On-Chip Distribution Architecture (IEEE Computer Society).pdf

1、IEEE Standard for High-Speed Test Access Port and On-Chip Distribution Architecture Sponsored by the Test Technology Standards Committee IEEE 3 Park Avenue New York, NY 10016-5997 USA IEEE Computer Society IEEE Std 1149.10-2017 IEEE Std 1149.10-2017 IEEE Standard for High-Speed Test Access Port and

2、On-Chip Distribution Architecture Sponsor Test Technology Standards Committee of the IEEE Computer Society Approved 18 May 2017 IEEE-SA Standards Board 2 Abstract: Circuitry that may be built into an integrated circuit to assist in the test, maintenance, and support of assembled printed circuit boar

3、ds, assembled multi-die packages, and the test of die internal circuits is defined in this standard. The circuitry includes a high-speed TAP (HSTAP) with a packet encoder/decoder and distribution architecture through which instructions and test data are communicated. The standard leverages the langu

4、ages of IEEE Std 1149.1 to describe and operate the on-chip circuits. Keywords: 3D-IC, Boundary-Scan Description Language, BSDL, debug, High Speed JTAG, I2C, IEEE 1149.1, PDL, IEEE 1149.10, integrated circuit, JTAG, waf er, Procedural Description Language, SERDES, SPI, system level test xThe Institu

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34、ormation may be obtained from the IEEE Standards Association. 6 Copyright 2017 IEEE. All rights reserved. Participants At the time this IEEE standard was completed, the P1149.10 Working Group had the following membership: C. J. Clark, Chair and Editor Bill Tuthill, Secretary Gobinathan Athimolom Tap

35、an Chakraborty Jonathon E. Colburn Heiko Ehrenberg Josh Ferry Bob Gottlieb Gurgen Harutyunyan Marc Hutner Dharma Konda Adam W. Ley Mike Ricchetti Craig Stephan Stephen Sunter Brian Turmelle The following members of the individual balloting committee voted on this standard. Balloters may have voted f

36、or approval, disapproval, or abstention. Saman Adham Gobinathan Athimolom Bill Brown William Bush Juan Carreon Tapan Chakraborty Keith Chow C. J. Clark Jonathon E. Colburn Glenn Colon-Bonet Adam Cron Jason Doege Heiko Ehrenberg William Eklow Josh Ferry Joel Goergen Bob Gottlieb Randall Groves Peter

37、Harrod Gurgen Harutyunyan Werner Hoelzl Marc Hutner Piotr Karocki Dharma Konda Philippe Lebourg Adam W. Ley Jeffrey Moore Charles Ngethe Jim OReilly Mike Ricchetti Craig Stephan Walter Struppler Stephen Sunter David Thompson Bill Tuthill Louis Ungar Oren Yuen When the IEEE-SA Standards Board approve

38、d this standard on 18 May 2017, it had the following membership: Jean-Philippe Faure, Chair Gary Hoffman, Vice Chair John D. Kulick, Past Chair Konstantinos Karachalios, Secretary Chuck Adams Masayuki Ariyoshi Ted Burse Stephen Dukes Doug Edwards J. Travis Griffith Michael Janezic Thomas Koshy Josep

39、h L. Koepfinger* Kevin Lu Daleep Mohla Damir Novosel Ronald C. Petersen Annette D. Reilly Robby Robson Dorothy Stanley Adrian Stephens Mehmet Ulema Phil Wennblom Howard Wolfman Yu Yuan *Member Emeritus 7 Copyright 2017 IEEE. All rights reserved. Introduction This introduction is not part of IEEE Std

40、 1149.10-2017, IEEE Standard for High-Speed Test Access Port and On-Chip Distribution Architecture. With the approval of IEEE Std 1149.1-2013, the industry now has a standardized approach to hierarchical design-for-test. IEEE Std 1149.1-2013 provides access to IP blocks via IEEE 1500 wrapper serial

41、ports. IEEE 1149.1 package files and PDL standardized how to describe IP block operation destined for SoC integration. Some Working Group members started to discuss the bandwidth limitations of the IEEE 1149.1 TAP, the limitations of single scan-in/scan-out for test time, the diminishing single-ende

42、d I/O count for parallel scan due to die-stacking, and the desire for leveraging PDL to be re-used beyond the TAP. A group of interested parties was formed in August of 2013. C. J. Clark presented the fundamentals on the HSTAP, PEDDA, and Packet format at the first meeting. Industry-based SERDES pac

43、kets were discarded because they required storing packet information in memory and generally required more on-chip resources. The IEEE 1149.10 architecture needed to be simple and easy to add on to the mission mode design. A PAR was approved in October 2013. A publicly available history of the Worki

44、ng Groups attendance, motions, minutes, and presentations can be found at http:/grouper.ieee.org/groups/1149/10/. 8 Copyright 2017 IEEE. All rights reserved. Contents 1. Overview 11 1.1 Scope . 11 1.2 Need . 11 1.3 Document outline 12 1.4 Specifications 12 1.5 Descriptions . 12 1.6 Text conventions

45、13 1.7 Logic diagram conventions 13 2. Normative references 14 3. Definitions, abbreviations, acronyms, and special terms 14 3.1 Definitions . 14 3.2 Abbreviations and acronyms . 16 3.3 Numbers 18 4. High-speed test access port (HSTAP) 18 4.1 HSTAP 18 5. Packet encoder/decoder and distribution archi

46、tecture 21 5.1 PEDDA 21 6. Packet definitions . 27 6.1 Packet overview . 27 6.2 The CONFIG packet 30 6.3 The TARGET packet . 32 6.4 The RESET packet 33 6.5 The RAW packet . 35 6.6 The CH-SELECT packet . 36 6.7 The SCAN packet 38 6.8 The BOND packet . 46 6.9 The CONFIGR packet . 47 6.10 The TARGETR p

47、acket 48 6.11 The RESETR packet 49 6.12 The RAWR packet . 50 6.13 The CH-SELECTR packet 51 6.14 The SCANR packet . 52 6.15 The BONDR packet . 56 7. BSDL definitions 57 7.1 BSDL overview . 57 7.2 Conformance attribute . 59 7.3 HSTAP attribute 59 7.4 Packet_Map attribute . 67 7.5 Control_Chars attribu

48、te . 71 7.6 Scan_Channel_Association attribute . 73 7.7 BSDL package for high speed JTAG 76 8. Channel bonding . 77 8.1 Optimizing bandwidth . 77 9 Copyright 2017 IEEE. All rights reserved. 9. PDL 82 9.1 PDL Overview . 82 9.2 iConfig command 83 9.3 iTarget command . 84 9.4 iReset10 command 85 9.5 iR

49、aw command 86 9.6 iBond command . 87 9.7 Standardized PDL procedures . 88 10. Compliance verification . 89 10.1 Overview . 89 Annex A (informative) Bibliography . 94 List of Figures Figure 1Logic symbology used in this standard . 14 Figure 2State diagram for IEEE 1149.10 entry . . 19 Figure 3Example daisy chain of HSTAPs 20 Figure 4System that benefits from the compliance-enable charac ter . 21 Figure 5Example IEEE 1149.10 PEDDA block diagram . 22 Figure 6Example implementati on of TRST10* and Reset10* . 25 Figure 7Example IEEE 1149.1 TDR for asserting Enable_1