IEEE 1296-1994 en Information Technology - Microprocessor Systems - High-Performance Synchronous 32-Bit Bus MULTIBUS II (IEEE Computer Society Document ISO IEC .pdf

1、iISO/IEC 10861 : 1994ANSI/IEEE Std 1296, 1994 EditionInformation technologyMicroprocessor systemsHigh-performance synchronous32-bit bus: MULTIBUS IISponsorTechnical Committee on Microprocessors and Microcomputersof theIEEE Computer SocietyAdopted as an International Standard by theInternational Orga

2、nization for Standardizationand by theInternational Electrotechnical CommissionPublished byThe Institute of Electrical and Electronics Engineers, Inc.iiAbstract: The operation, functions, and attributes of a parallel system bus (PSB), called MULTIBUS II, aredefined. A high-performance backplane bus

3、intended for use in multiple processor systems, the PSBincorporates synchronous, 32-bit multiplexed address/data, with error detection, and uses a 10 MHz busclock. This design is intended to provide reliable state-of-the-art operation and to allow the implementationof cost-effective, high-performanc

4、e VLSI for the bus interface. Memory, I/O, message, and geographicaddress spaces are defined. Error detection and retry are provided for messages. The message-passingdesign allows a VLSI implementation, so that virtually all modules on the bus will utilitze the bus at itshighest performance32 to 40

5、Mbyte/s. An overview of PSB, signal descriptions, the PSB protocol,electrical characteristics, and mechanical specifications are covered.Keywords: high-performance sychronous 32-bit bus, MULTIBUS II, system bus architecturesThe Institute of Electrical and Electronics Engineers, Inc.345 East 47th Str

6、eet, New York, NY 10017-2394, USACopyright 1994 by the The Institute of Electrical and Electronics Engineers, Inc.All rights reserved. Published 1994. Printed in the United States of America.ISBN 1-55937-368-7No part of this publication may be reproduced in any form, in an electronic retrieval syste

7、m or otherwise, without theprior written permission of the publisher.iiiForewordISO (the International Organization for Standardization) and IEC (the International Electrotechnical Commission)form the specialized system for worldwide standardization. National bodies that are members of ISO or IECpar

8、ticipate in the development of International Standards through technical committees established by the respectiveorganization to deal with particular fields of technical activity. ISO and IEC technical committees collaborate in fieldsof mutual interest. Other international organizations, governmenta

9、l and nongovernmental, in liaison with ISO and IEC,also take part in the work.In the field of information technology, ISO and IEC have established a joint technical committee, ISO/IEC JTC 1.Draft International Standards adopted by the joint technical committee are circulated to national bodies for v

10、oting.Publication as an International Standard requires approval by at least 75% of the national bodies casting a vote.In 1990, ANSI/IEEE Std 1296-1987 was adopted by ISO/IEC JTC 1, as draft International Standard ISO/IEC/DIS10861. This draft was subsequently approved by ISO/IEC JTC 1 in the form of

11、 this edition, which is published asInternational Standard ISO/IEC 10861 : 1994.International Organization for Standardization/International Electrotechnical CommissionCase postale 56 CH-1211 Genve 20 SwitzerlandivIEEE Standards documents are developed within the Technical Committees of the IEEE Soc

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19、vide an instant response to interpretation requestsexcept in those cases where the matter has previously received formal consideration.Comments on standards and requests for interpretations should be addressed to:Secretary, IEEE Standards Board445 Hoes LaneP.O. Box 1331Piscataway, NJ 08855-1331USAIE

20、EE standards documents may involve the use of patented technology. Their approval by the Institute ofElectrical and Electronics Engineers does not mean that using such technology for the purpose of conforming tosuch standards is authorized by the patent owner. It is the obligation of the user of suc

21、h technology to obtain allnecessary permissions.vIntroduction(This introduction is not a normative part of ISO/IEC 10861 : 1994 ANSI/IEEE Std 1296, 1994 Edition, but is included forinformation only.)In the last decade, the avalanche of new microcomputer technology, especially VLSI, threatened to obs

22、olete productsalmost before they went into production. To buffer users from this onrush of technology, Intel helped develop standardinterfaces. One of the most notable was the MULTIBUS I system bus, which was used as the basis for a standard bythe IEEE in 1983 as IEEE Std 796-1983 (after going throu

23、gh a 5-year review and revision process).In the early 1980s, Intel recognized that the trends toward multiprocessing and more sophisticated microcomputer-based systems called for an advanced 32-bit system bus architecture. Intel called this new bus MULTIBUS II. Incontinuing to pioneer the open syste

24、ms technology, which included multiprocessing, four critical requirements wereobserved: technical credibility, processor independence, standardization, and openness to all levels of integration.Early in the development of the new bus, Intel established a “MULTIBUS II Development Consortium.” Thecons

25、ortium gave the new bus a technical credibility that few buses, especially those defined only among board vendors,can match. The companies in the consortium also represented all microprocessor families; included in the group were68020, 32032, 80386, and Z8000 board and system users, thus ensuring th

26、at the bus is easily adaptable to virtually anymanufacturers processor.The primary benefits being sought in the creation of this new bus were high-performance multiprocessing, high systemreliability, ease-of-use by system designers, and improved cost/performance.Specific bus features were developed

27、in response to these objectives. The 32 Mbyte/s message passing of the busprovides a bus that acts like a very high-speed network connection for multiple processors (or processor equivalents).There is a recognition that the bus is no longer to interconnect a CPU with its memory and I/O; instead the

28、bus is tointerconnect whole stand-alone processors with each other and with intelligent “subsystems-on-a-board.”System reliability is enhanced by the features of bus parity, synchronous operation, negative acknowledge, transferretries, geographic addressing, and advanced backplane design. Ease-of-us

29、e by system designers is implementedprimarily through the geographic addressing, which provides for dynamic system configuration. The bus encouragesthe use of software programmable configuration options (and discourages any use of mechanical jumpers). Thestandardization of the high-level message-pas

30、sing protocol also gives the system designer an easy-to-use capability forinterprocessor communication.The cost/performance objective of the bus is delivered through its specification of a realizable 32 to 40 Mbyte/s busbandwidth. Virtually all boards designed to the bus can achieve this bus utiliza

31、tion factor due to the high-level protocolcalled out in the specification, and thus the availability of standard, high-performance and cost-effective VLSIcomponents to actually implement this level of performance. For example, this specification and the VLSI make itpossible for eight concurrent 4 me

32、gabyte/second transfers to take place on the bus. This, or other combinations oftransfers that add up to 32 Mbyte/s, demonstrate the real cost/performance advantages of the bus for multiprocessorapplications.In 1983 MULTIBUS II was introduced to the IEEE standards process as a part of the considerat

33、ions for the P896(Future Bus) working group activities. In the 1984/1985 time frame the MSC (Microcomputer Standards Committee,of the TCMM) formed an independent study group for MULTIBUS II. During this time the many active participantsof the group proceeded to thoroughly review and make changes to

34、the proposed draft. In early 1986 the group wasassigned a formal project number P1296. During the remainder of 1986, the draft was passed by the Working Groupand the MSC after thorough review, discussion, and changes. In 1987, the draft was presented for Sponsor ballot and,after passing, presented t

35、o the June 1987 meeting of the IEEE Standards Board.The IEEE Standards Board calls attention to the fact that there are patents claimed and/or pending on many aspects ofthis bus by Intel Corporation. IEEE takes no position with respect to patent validity. Intel Corporation has assured theIEEE that i

36、t is willing to grant a license for these patents on reasonable and nondiscriminatory terms to anyone wishingvito obtain such a license. The general terms of the license are a one-time administration fee of $100 for a nonexclusiveperpetual license. Intel Corporations undertakings in this respect are

37、 on file obtained from the legal department ofIntel Corporation whose address is Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124.There were many contributors to the standards review process, but the following members deserve special mention fortheir active participation:The P129

38、6 Working Group that prepared this standard had the following membership:Richard W. Boberg, Chair Web AugustineJack BlevinsPaul BorrillSteve CooperTom CrawfordGene FreehaufMaurice HubertHubert KirrmannKlaus MuellerJim NebusDon NickelKen SmithMichael ThompsonScott TetrickEike WaltzJanusz ZalewskiThe

39、following members of the Technical Committee on Microprocessors and Microcomputers were on the ballotingbody:Andrew AllisonPeter J. AshendenMatt BiewerJohn BlackJack BlevinsRichard BobergPaul BorrillBradley BrownClyde CampJohn D. CharltonSteve CooperRandy DavisJ. Robert DavisShirish P. DeodharJim Du

40、nlayWayne FischerJim FlournoyGordon ForceMartin FreemanDavid GustavsonTom HarkawayDave HawleyDavid JamesLaurel KaledaRichard KarpinskiHubert KirrmanDoug KraftTom KuriharaGlen LangdonGerry LawsTom LeonardRollie LinserGary LyonsJames NebusGary NelsonDeene OgdenTom PittmanShlomo Pri-TalP. ReghunathanRi

41、chard RawsonBill ShieldsMichael SmolinRobert StewartSubramanganesanMichael TeenerScott TetrickEike WaltzCarl WarrenGeorge WhiteFritz WhittingtonTom WicklundAndrew WilsonAnthony WinterTask Force Coordinators: Jack BlevinsMaurice HubertHubert KirrmannJim NebusSecretary of Working Group: Steve CooperOr

42、iginal Study Group Chairman: Paul BorrillOriginal Draft Editor: Scott TetrickviiWhen the IEEE Standards Board approved this standard on June 11, 1987, it had the following membership:Donald C. Fleckenstein, Chair Marco W. Migliaro, Vice Chair Andrew G. Salem, Secretary James H. BeallDennis BodsonMar

43、shall L. CainJames M. DalyStephen R. DillonEugene P. FogartyJay ForsterKenneth D. HendrixIrvin N. HowellLeslie R. KerrJack KinnIrving KolodnyJoseph L. Koepfinger*Edward LohseJohn MayLawrence V. McCallL. Bruce McClungDonald T. Michael*L. John RankineJohn P. RiganatiGary S. RobinsonFrank L. RoseRobert

44、 E. RountreeSava I. Sherr*William R. TackaberryWilliam B. WilkensHelen M. Wood*Member EmeritusIEEE Std 1296-1987 was approved by the American National Standards Institute on February 8, 1987 and wasreaffirmed by IEEE on March 17, 1994.viiiCLAUSE PAGE1. General overview 11.1 Scope 11.2 Normative refe

45、rences . 12. Definitions.23. Guide to notation.53.1 General . 53.2 Signal notation . 53.3 Figure notation . 53.4 Notation in state-flow diagrams. 63.5 Notation for multiple bit data representation . 64. PSB overview74.1 General . 74.2 Address/data path and system control signals 84.3 Message-passing

46、 facility 84.4 Interconnect facility . 84.5 Synchronous operation of the PSB 84.6 Bus operations on the PSB. 84.7 Central services module . 125. Signal descriptions 125.1 General . 125.2 Signal groups 126. PSB protocol .206.1 General . 206.2 Arbitration operation 216.3 Transfer operation 316.4 Excep

47、tion operation . 526.5 Central control functions 566.6 State-flow diagrams . 637. Electrical characteristics .767.1 General . 767.2 AC timing specifications 777.3 DC specifications for signals . 847.4 Current limitations per connector 857.5 Pin assignments 868. Mechanical specifications .898.1 Gener

48、al . 898.2 Board sizes and dimensions . 908.3 Printed board layout considerations. 91ixCLAUSE PAGE8.4 Front panel . 918.5 Connectors . 918.6 Backplanes . 929. IEEE 1296 System Interface specification1009.1 Overview 1009.2 Interconnect space operation 1019.3 I/O space operation 1169.4 Memory space op

49、erations 1179.5 Message space operations 11710. IEEE 1296 capabilities12810.1 Characteristic codes . 128Annex A (Informative) Recommended documentation practices.1291Information technologyMicroprocessor systemsHigh-performance synchronous 32-bit bus: MULTIBUS II1. General overview1.1 ScopeThis International Standard defines the operation, functions, and attributes of the IEEE 1296 bus standard.a) This standard defines a high-performance 32-bit synchronous bus standard.b) The bus standard must have a design-in lifetime of 10 years with backward compatibility.c) The standar