IEEE 1450 6 1-2009 en Describing On-Chip Scan Compression (IEEE Computer Society)《芯片上扫描压缩的描述》.pdf

1、IEEE Std 1450.6.1-2009IEEE Standard for DescribingOn-Chip Scan CompressionIEEE3 Park Avenue New York, NY 10016-5997, USA13 July 2009IEEE Computer SocietySponsored by theTest Technology Standards Committee1450.6.1TMIEEE Std 1450.6.1-2009IEEE Standard for Describing On-Chip Scan CompressionSponsorTest

2、 Technology Standards Committeeof theIEEE Computer SocietyApproved 13 May 2009IEEE-SA Standards BoardAbstract: This standard defines how the necessary information is passed from scan insertion topattern generation and from pattern generation to diagnosis such that different tool vendors couldbe used

3、 for each step independent of on-chip scan compression logic used.Keywords: chip design, design automation, on-chip scan compression, pattern generation, scaninsertionThe Institute of Electrical and Electronics Engineers, Inc.3 Park Avenue, New York, NY 10016-5997, USACopyright 2009 by the Institute

4、 of Electrical and Electronics Engineers, Inc.All rights reserved. Published 13 July 2009. Printed in the United States of America.IEEE is a registered trademark in the U.S. Patent +1 978 750 8400. Permission to photocopy portions of any individual standard for educationalclassroom use can also be o

5、btained through the Copyright Clearance Center.iv Copyright 2009 IEEE. All rights reserved.IntroductionThe purpose of this standard is to provide a sufficient description of on-chip scan compression structures,operation, and connectivity such that EDA tools may interoperate for pattern generation an

6、d diagnosis. Thestandard extends the CTL language (IEEE Std 1450.6), which provides such information for designs withouton-chip scan compression structures.Notice to usersLaws and regulationsUsers of these documents should consult all applicable laws and regulations. Compliance with theprovisions of

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13、e.org/reading/ieee/updates/errata/index.html. Users are encouraged to check this URL forerrata periodically.This introduction is not part of IEEE Std 1450.6.1-2009, IEEE Standard for Describing On-Chip Scan Compression.Copyright 2009 IEEE. All rights reserved. vInterpretationsCurrent interpretations

14、 can be accessed at the following URL: http:/standards.ieee.org/reading/ieee/interp/index.html.PatentsAttention is called to the possibility that implementation of this standard may require use of subject mattercovered by patent rights. By publication of this standard, no position is taken with resp

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17、 is entirely their own responsibility. Further informationmay be obtained from the IEEE Standards Association.vi Copyright 2009 IEEE. All rights reserved.ParticipantsAt the time this standard was submitted to the IEEE-SA Standards Board for approval, the OCI (Open Com-pression Interface) Working Gro

18、up had the following membership: Bruce Cory (NVIDIA), Chair The following members of the entity balloting committee voted on this standard. Balloters may have votedfor approval, disapproval, or abstention. When the IEEE-SA Standards Board approved this standard on 13 May 2009, it had the followingme

19、mbership:Robert M. Grow, ChairThomas Prevost, Vice ChairSteve M. Mills, Past ChairJudith Gorman, Secretary*Member EmeritusAlso included are the following nonvoting IEEE-SA Standards Board liaisons:Howard L. Wolfman, TAB RepresentativeMichael Janezic, NIST RepresentativeSatish Aggarwal, NRC Represent

20、ativeLorraine PatscoIEEE Standards Program Manager, Document DevelopmentMichael KipnessIEEE Standards Program Manager, Technical Program DevelopmentDwayne Burek (Magma)Phil Burlison (Verigy)Al Crouch (Asset Intertech)Manish Dandekar (Intel)Geir Eide (Magma)Rohit Kapur (Synopsys)Mark Kassab (Mentor G

21、raphics)Brion Keller (Cadence)Kee Sup Kim (Intel)Steve Oakland (IBM)Rolf Schlagenhaft (Freescale)Accellera Cadence Design Intel Mentor Graphics Nvidia Synopsys John BarrKaren BartlesonVictor BermanTed BurseRichard DeBlasioAndy DrozdMark EpsteinAlexander GelmanJim HughesRichard H. HulettYoung Kyun Ki

22、mJoseph L. Koepfinger*John KulickDavid J. LawTed OlsenGlenn ParsonsRonald C. PetersenNarayanan RamachandranJon Walter RosdahlSam SciaccaCopyright 2009 IEEE. All rights reserved. viiContents1. Overview. 11.1 Scope 11.2 General . 11.3 Conceptual data flow 21.4 High-level implementation details . 31.5

23、Limitations of this standard 51.6 Structure of this standard 52. Normative references 63. Definitions, acronyms, and abbreviations 63.1 Definitions 63.2 Acronyms and abbreviations 64. New blocksCompressionStructures 74.1 CompressionStructures block. 74.2 CompressionStructures block syntax descriptio

24、n 74.3 CompressionStructures block example 85. STIL blockextensions to IEEE Std 1450-1999, Clause 8. 95.1 STIL syntax 95.2 STIL syntax description . 95.3 STIL syntax example . 96. Environment blockextensions to IEEE Std 1450.1-2005, Clause 17 . 106.1 Environment block . 106.2 Environment block synta

25、x description . 106.3 Environment block example. 127. Semantics updates. 12Annex A (informative) Examples 14Copyright 2009 IEEE. All rights reserved. 1IEEE Standard for Describing On-Chip Scan CompressionIMPORTANT NOTICE: This standard is not intended to ensure safety, security, health, or environme

26、ntal protection in all circumstances. Implementers of the standard are responsible for determining appropriate safety, security, environmental, and health practices or regulatory requirements.This IEEE document is made available for use subject to important notices and legal disclaimers. These notic

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28、Overview1.1 ScopeThis standard defines how the necessary information is passed from scan insertion to pattern generation and from pattern generation to diagnosis such that different tool vendors could be used for each step independent of on-chip scan compression logic used.1.2 GeneralFlows for scan-

29、based test tools are broken into three main stages. Test logic insertion, pattern generation, and diagnosis. Test logic insertion does insertion and verification of test logic. Pattern generation uses the test logic to make test patterns that can be used to verify if the design is fabricated correct

30、ly. Diagnosis is used to identify the failing location in a specific device. Diagnosis information can also be used to increase future yield and to solve problems that keep a design from going to market.This standard, the Open Compression Interface (OCI), defines on-chip scan compression structures

31、(OCSCS), which can be used to pass information from test logic insertion to pattern generation, and from pattern generation to diagnosis, such that interoperability of electronic design automation (EDA) tools is possible. These structures Only reveal as much hardware implementation as necessary for

32、pattern generation and diagnosis Do not limit EDA companies from innovating and developing their own compression solutionsIEEE Std 1450.6.1-2009 IEEE STANDARD FOR DESCRIBING2 Copyright 2009 IEEE. All rights reserved. Support most types of structures for input and output compressionOCSCS are defined

33、here as an extension of IEEE Std 1450.6TM-2005 Core Test Language (CTL).1This standard highlights the revised CTL syntax and then provides several examples that cover common compression structure types. The actual OCI syntax and semantics appear prior to the examples.1.3 Conceptual data flowFigure 1

34、 shows the OCI conceptual data flow from test logic insertion to pattern generation and from pattern generation to diagnosis. Both the OCI flow (assuming a different vendor for each stage) and the current flow (same vendor for each stage) are shown. Since same-vendor tools have their own way of link

35、ing different stages of the flow together, OCI is only needed for changing stages when any previous step was completed by a different vendor. If different vendors were used, then all the data OCI would normally add in the previous stages is needed.Figure 1Conceptual OCI flowThe test logic insertion

36、stage has the best understanding of the test structure being implemented. Test logic insertion tools are developed based on specific compression structures and have many special design rule checks implemented so customers have as good a chance as possible to generate working, highly effective patter

37、ns the first time. The time and knowledge necessary to develop all of the design rule checks is significant. Due to this, the OCI flow presumes the pattern generation tool does not need to perform test structure verification. In the case where a design house is integrating a core with in-house desig

38、n logic, the test structure in the core is presumed to be verified by the core provider and all core-level OCI information needed for pattern generation shall be in the OCI-compliant CTL file the core provider gives the design house. The design house integrating the core is responsible for generatin

39、g and verifying the final OCI information passed to pattern generation.The OCI-specific information passed from test logic insertion to pattern generation includes pattern sequence restrictions, a description of compression hardware, netlist mapping points, and vendor-specific data to ensure vendor

40、flows are as easy to use as possible when using OCI. For a more detailed description of how CTL is leveraged to pass information from test logic insertion to pattern generation, see 1.4.The pattern generation stage can be very time consuming. The automatic test pattern generator (ATPG) determines wh

41、ich logic values are needed on scan cells to detect the most faults by each test pattern. After a pattern is generated, it is then simulated to determine how many faulty locations have been detected. This 1For information on references, see Clause 2.OCI Transfer Data Test Logic Insertion Pattern Gen

42、eration Diagnosis OCI Transfer Data Current OCI Inserts test structuresVerifies test structures (DRC) Adds information for Pattern Generation - Allowed Sequences - Compression structure description - Symbolic to netlist name mapping Assumes IP implemented correctlyUses equations and sequences Writes

43、 out pattern data Add information for Diagnosis - identify key events Uses patterns, sequences, and event identifiers- calculate failing defect candidates ON-CHIP SCAN COMPRESSION IEEE Std 1450.6.1-2009Copyright 2009 IEEE. All rights reserved. 3sequence is repeated until as many as possible faulty l

44、ocations have been detected. For chips without on-chip scan compression, the value loaded and unloaded from each scan cell can be mapped directly to a unique value loaded into the chip and to a unique value unloaded from the chip. Only sequence definitions that describe how to initialize, load, unlo

45、ad, and apply tests are needed by pattern generation for this case.On-chip scan compression needs more information. Putting a logic value in a scan cell requires a value to be loaded into the chip at a previous point in time and likely forces other scan cells to be put to certain logic values. Check

46、ing that a value is in a scan cell may require values in masking logic or on other scan cells. Also, on-chip scan compression hardware may restrict the length of a sequence or require a relationship between sequences because of how the hardware is implemented. To do pattern generation efficiently, O

47、CI passes pattern generation sequences, sequence limitations/relationships, and symbolic descriptions of the compression hardware created by the test logic insertion stage.The output test patterns generated by pattern generation need to be diagnosable using both EDA diagnosis, that can isolate to a

48、gate or net, and on the tester, where isolation is possible due to the failing scan cell or scan chain. To enable this capability, the pattern generation stage shall identify key events in the pattern data and pass this information to diagnosis. The information is passed through OCI by updating the

49、sequences and/or by adding information to the test pattern data. For a more detailed description of how CTL is leveraged to pass information from pattern generation to diagnosis, see 1.4.The diagnosis stage uses the key event information added by pattern generation to map each automatic test equipment (ATE) failure back to a list of defect candidates that might have caused that failure. The diagnosis stage does not add any new information to the OCI file.1.4 High-level implementation detailsOCI data is passed from stage to stage to allow tool interoperability. T