IEEE 1481-2009 en Integrated Circuit (IC) Open Library Architecture (OLA) (IEEE Computer Society)《集成电路(IC)开放性库结构(OLA)》.pdf

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3、78g3g36g89g72g81g88g72g3g49g72g90g3g60g82g85g78g15g3g49g60g3g20g19g19g20g25g16g24g28g28g26g15g3g56g54g36g3g3g20g20g3g48g68g85g70g75g3g21g19g20g19g20g23g27g20g55g48IEEE Std 1481TM-2009(Revision of IEEE Std 1481-1999)IEEE Standard for Integrated Circuit (IC) Open Library Architecture (OLA)SponsorDesig

4、n Automation Standards Committeeof theIEEE Computer Society9 December 2009IEEE-SA Standards Board Royalty-free nonexlcusive permission has been granted by International Business Machines(IBM) Corporation for all written contributions made by IBM under the direction of Harry J. BeattyIII.Royalty-free

5、 permission has been granted by Silicon Integration Initiative, Inc. (Si2) to reprintmaterial from Specification for the Open Library Architecture (OLA), Version 2.0-00, March 1,2003.Abstract: Ways for integrated circuit designers to analyze chip timing and power consistentlyacross a broad set of el

6、ectric design automation (EDA) applications are covered in this standard.Methods by which integrated circuit vendors can express timing and power information once pergiven technology are also covered. In addition, the means by which EDA vendors can meet theirapplication performance and capacity need

7、s are discussed.Keywords: chip delay, electronic design automation (EDA), integrated circuit (IC) design, powercalculationThe Institute of Electrical and Electronics Engineers, Inc. 3 Park Avenue, New York, NY 10016-5997, USA Copyright 2010 by the Institute of Electrical and Electronics Engineers, I

8、nc. All rights reserved. Published 11 March 2010. Printed in the United States of America.IEEE is a registered trademark in the U.S. Patent +1 978 750 8400. Permission to photocopy portions of any individual standard foreducational classroom use can also be obtained through the Copyright Clearance C

9、enter.IntroductionThe objective of the delay and power calculation system (DPCS) is to make it possible for integrated circuitdesigners to consistently calculate chip delay and power across electronic design automation (EDA)applications and for integrated circuit vendors to express delay and power i

10、nformation only once pertechnology while enabling sufficient EDA application accuracy.This is accomplished by a coordinated set of standards that support a standard method to describe timingand power characteristics of integrated circuit design units (cells and higher level design elements); astanda

11、rd method for EDA applications to calculate chip design instance specific delay, slew, and power forlogic and interconnects; and standard file formats to exchange chip parasitic and cluster information.Notice to usersLaws and regulationsUsers of these documents should consult all applicable laws and

12、 regulations. Compliance with theprovisions of this standard does not imply compliance to any applicable regulatory requirements.Implementers of the standard are responsible for observing or referring to the applicable regulatoryrequirements. IEEE does not, by the publication of its standards, inten

13、d to urge action that is not incompliance with applicable laws, and these documents may not be construed as doing so.CopyrightsThis document is copyrighted by the IEEE. It is made available for a wide variety of both public andprivate uses. These include both use, by reference, in laws and regulatio

14、ns, and use in private self-regulation, standardization, and the promotion of engineering practices and methods. By making thisdocument available for use and adoption by public authorities and private users, the IEEE does not waiveany rights in copyright to this document.Updating of IEEE documentsUs

15、ers of IEEE standards should be aware that these documents may be superseded at any time by theissuance of new editions or may be amended from time to time through the issuance of amendments,corrigenda, or errata. An official IEEE document at any point in time consists of the current edition of thed

16、ocument together with any amendments, corrigenda, or errata then in effect. In order to determine whethera given document is the current edition and whether it has been amended through the issuance ofamendments, corrigenda, or errata, visit the IEEE Standards Association Web site athttp:/ieeexplore.

17、ieee.org/xpl/standards.jsp, or contact the IEEE at the address listed previously.For more information about the IEEE Standards Association or the IEEE standards development process,visit the IEEE-SA Web site at http:/standards.ieee.org.ErrataErrata, if any, for this and all other standards can be ac

18、cessed at the following URL:http:/standards.ieee.org/reading/ieee/updates/errata/. Users are encouraged to check this URL for errataperiodically.ivCopyright 2010 IEEE all rights reserved.This introduction is not part of IEEE Std 1481-2009, IEEE Standard for Integrated Circuit (IC) Open Library Archi

19、tecture (OLA).InterpretationsCurrent interpretations can be accessed at the following URL: http:/standards.ieee.org/reading/ieee/interp/.PatentsAttention is called to the possibility that implementation of this standard may require use of subject mattercovered by patent rights. By publication of thi

20、s standard, no position is taken with respect to the existenceor validity of any patent rights in connection therewith. A patent holder or patent applicant has filed astatement of assurance that it will grant licenses under these rights without compensation or underreasonable rates, with reasonable

21、terms and conditions that are demonstrably free of any unfairdiscrimination to applicants desiring to obtain such licenses. Other Essential Patent Claims may exist forwhich a statement of assurance has not been received. The IEEE is not responsible for identifying EssentialPatent Claims for which a

22、license may be required, for conducting inquiries into the legal validity or scopeof Patents Claims, or determining whether any licensing terms or conditions are reasonable or non-discriminatory. Further information may be obtained from the IEEE Standards Association.vCopyright 2010 IEEE all rights

23、reserved.ParticipantsAt the time this trial-use standard was submitted to the IEEE-SA Standards Board, the Integrated Circuit(IC) Open Library Architecture (OLA) Working Group had the following membership:Harry J. Beatty III, ChairTimothy J. Ehrler, Vice Chair Sandeep BhutaniShir-Shen ChangSumit Das

24、GuptaAntenor de CarvalhoStacy DossMartin FoltinMark HahnRobert C. KezerArchie LachnerTimothy LehnerChiYuan LoDaniel MoritzJoseph MorrellTina NevinSteve RaykoBernard SheehanJayesh SiddhiwalaOlivier TouzetEmre TuncerJim WilmoreThe following members of the balloting committee voted on this trial-use st

25、andard. Balloters may havevoted for approval, disapproval, or abstention. Harry J. Beatty IIIVictor BermanKeith ChowEllis CohenThomas DineenTimothy J. EhrlerRandall GrovesWerner HoelzlCharles NgetheUlrich PohlBartian SayogoStephen SchwarmWalter StrupplerSrinivasa VemuruOren YuenWhen the IEEE-SA Stan

26、dards Board approved this standard on 9 December 2009, it had the followingmembership:Robert M. Grow, ChairThomas Prevost, Vice ChairSteve M. Mills, Past ChairJudith Gorman, SecretaryJohn BarrKaren BartlesonVictor BermanTed BurseRichard DeBlasioAndy DrozdMark EpsteinAlexander GelmanJim HughesRichard

27、 H. HulettYoung Kyun KimJoseph L. Koepfinger*John KulickDavid J. LawTed OlsenGlenn ParsonsRonald C. PetersenNarayanan RamachandranJon Walter RosdahlSam Sciacca*Member EmeritusAlso included are the following nonvoting IEEE-SA Standards Board liaisons:Howard L. Wolfman, TAB RepresentativeMichael Janez

28、ic, NIST RepresentativeSatish K. Aggarwal, NRC RepresentativeLorraine PatscoIEEE Standards Program Manager, Document DevelopmentMichael D. KipnessIEEE Standards Program Manager, Technical Program DevelopmentviCopyright 2010 IEEE all rights reserved.Contents1 Overview.11.1 Scope11.2 Purpose.21.3 Intr

29、oduction22 Normative references33 Definitions44 Acronyms and abbreviations.135 Typographical conventions.145.1 Syntactic elements145.2 Conventions.156 DPCS flow166.1 Overview166.1.1 Procedural interface.176.1.2 Global policies and conventions176.2 Flow of control.176.3 DPCMapplication relationships.

30、186.3.1 Technology library.186.3.2 Subrule.186.4 Interoperability.187 Delay calculation language (DCL).197.1 Character set.197.2 Lexical elements197.2.1 Whitespace197.2.2 Comments197.2.3 Tokens197.2.4 Header names317.2.5 Preprocessing directives317.3 Context.317.3.1 Space.317.3.2 Plane317.3.3 Contex

31、t operation317.3.4 Library parallelism317.3.5 Application parallelism327.4 Data types.327.4.1 Base types327.4.2 Native data types.327.4.3 Mathematical calculation data types.327.4.4 Pointer data types337.4.5 Aggregate data types.337.5 Identifiers.397.5.1 Name spaces of identifiers397.5.2 Storage dur

32、ations of objects397.5.3 Scope of identifiers407.5.4 Linkages of identifiers.417.6 Operator descriptions.417.6.1 String prefix operator417.6.2 Explicit string prefix operator.417.6.3 Embedded string prefix operator.427.6.4 String prefix semantics427.6.5 Assignment operator427.6.6 New operator.427.6.

33、7 SCOPE operator(s)43viiCopyright 2010 IEEE all rights reserved.7.6.8 Launch operator.447.6.9 Purity operator.447.6.10 Force operator457.7 Timing propagation457.7.1 Timing checks467.7.2 Test mode operators.467.8 Expressions487.8.1 Array subscripting.497.8.2 Statement calls.497.8.3 General syntax.497

34、.8.4 Method statement calls497.8.5 Assign variable reference507.8.6 Store variable reference.507.8.7 Mathematical expressions.507.8.8 Mathematical operators.517.8.9 Discrete math expression.527.8.10 INT discrete.527.8.11 PINLIST discrete.537.8.12 Logical expressions and operators537.8.13 MODE expres

35、sions537.8.14 Embedded C code expressions557.8.15 Computation order.567.9 DCL mathematical statements.587.9.1 Statement names587.9.2 Clauses.587.9.3 Modifiers.627.9.4 Prototypes647.9.5 Statement failure677.9.6 Type definition statements.677.9.7 Interfacing statements687.9.8 DCL to C communication.70

36、7.9.9 Constant statement717.9.10 Calculation statements.717.9.11 METHOD statement747.10 Predefined types.757.10.1 ACTIVITY_HISTORY_TYPE.757.10.2 HISTORY_TYPE767.10.3 LOAD_HISTORY_TYPE.777.10.4 CELL_LIST_TYPE.777.10.5 TECH_TYPE.787.10.6 DELAY_REC_TYPE787.10.7 SLEW_REC_TYPE787.10.8 CHECK_REC_TYPE787.1

37、0.9 CCDB_TYPE797.10.10 CELL_DATA_TYPE.797.10.11 PCDB_TYPE.797.10.12 PIN_ASSOCIATION797.10.13 PATH_DATA_TYPE.807.10.14 STD STRUCT.807.11 Predefined variables.807.11.1 ARGV807.11.2 CONTROL_PARM.817.12 Built-in function calls.817.12.1 ABS.817.12.2 Complex number components.817.12.3 EXPAND.82viiiCopyrig

38、ht 2010 IEEE all rights reserved.7.12.4 Array functions827.12.5 Messaging functions827.13 Tables.847.13.1 TABLEDEF statement.857.13.2 Table visibility rules877.13.3 TABLE statement877.13.4 LOAD_TABLE statement.917.13.5 UNLOAD_TABLE statement.937.13.6 WRITE_TABLE statement947.13.7 ADD_ROW statement.9

39、47.13.8 DELETE_ROW statement957.14 Built-in library functions967.14.1 Numeric conversion functions.967.14.2 Tech_family functions.987.14.3 Trigonometric functions997.14.4 Context manipulation functions997.14.5 Debug controls1017.14.6 Utility functions.1027.14.7 Table functions1027.14.8 Subrule contr

40、ols.1037.15 Library control statements.1047.15.1 Meta-variables.1057.15.2 TECH_FAMILY1057.15.3 RULENAME.1057.15.4 CONTROL_PARM.1057.15.5 SUBRULE statement1057.15.6 Path list expansion rules1067.15.7 SUBRULES statement1077.15.8 Control file1077.15.9 TECH_FAMILY statement1097.15.10 SUBRULE and SUBRULE

41、S statements.1097.16 Modeling1107.16.1 Types of modeling.1107.16.2 Model organization1117.16.3 MODELPROC statement1127.16.4 SUBMODEL statement.1137.16.5 Modeling statements1147.16.6 TEST_BUS statement.1247.16.7 INPUT statement.1247.16.8 OUTPUT statement.1287.16.9 DO statement.1297.16.10 PROPERTIES s

42、tatement.1537.16.11 SETVAR statement1547.17 Embedded C code1557.18 Definition of a subrule.1557.19 Pragma.1567.19.1 IMPORT_EXPORT_TAG.1568 Power modeling and calculation.1578.1 Power overview1578.2 Caching state information1588.2.1 Initializing the state cache.1588.2.2 State cache lifetime.1588.3 Ca

43、ching load and slew information.1588.3.1 Loading the load and slew cache.1598.3.2 Load and slew cache lifetime159ixCopyright 2010 IEEE all rights reserved.8.4 Simulation switching events1598.5 Partial swing events.1608.6 Power calculation.1608.7 Accumulation of power consumption by the design1628.8

44、Group Pin List syntax and semantics.1628.8.1 Syntax1628.8.2 Semantics.1628.8.3 Example.1638.9 Group Condition List syntax and semantics1638.9.1 Syntax1638.9.2 Semantics.1638.9.3 Example.1648.10 Sensitivity list syntax and semantics1648.10.1 Syntax1648.10.2 Semantics.1648.10.3 Example.1658.11 Group c

45、ondition language1658.11.1 Syntax1658.11.2 Semantics.1668.11.3 Condition expression operator precedence1688.11.4 Condition expressions referencing pin states and transitions1688.11.5 Semantics of nonexistent pins.1689 Application and library interaction.1709.1 behavior model domain1709.2 vectorTimin

46、g and vectorPower model domains1709.2.1 Power unit conversion.1709.2.2 Vector power calculation.17110 Procedural interface (PI).17210.1 Overview17210.1.1 DPCM17210.1.2 Application17210.1.3 libdcmlr.17210.2 Control and data flow.17310.3 Architectural requirements.17310.4 Data ownership technique17310

47、.4.1 Persistence of data passed across the PI17310.4.1 Data cache guidelines for the DPCM17410.4.2 Application/DPCM interaction17410.4.3 Application initializes message/memory handling17410.4.4 Application loads and initializes the DPCM.17410.4.5 Application requests timing models for cell instances

48、17510.5 Model domain issues17510.5.1 Model domain selection17510.5.2 Model domain determination17510.5.3 DPCM invokes application modeling callback functions.17510.5.4 Application requests propagation delay17610.5.5 DPCM calls application EXTERNAL functions.17710.6 Reentry requirements.17710.7 Appli

49、cation responsibilities when using a DPCM.17710.7.1 Standard Structure rules17710.7.2 User object registration.17710.7.3 Selection of early and late slew values17810.7.4 Semantics of slew values.17810.7.5 Slew calculations.179xCopyright 2010 IEEE all rights reserved.10.8 Application use of the DPCM17910.8.1 Initialization of the DPCM17910.8.2 Context creation18010.8.3 Dynamic linking18010.8.4 Subrule initialization.18110.8.5 Use of the DPCM18110.8.6 Application control18110.8.7 Application execution18210.8.8 Termination of DPCM.18210.9 DPCM library organization18210.9.1 M