IEEE 1596-1992 en Standard for Scalable Coherent Interface (SCI) (IEEE Computer Society Document)《可测量相干接口的标准(SCI)》.pdf

1、 Recognized as anAmerican National Standard (ANSI)IEEE Std 1596-1992(Adopted by ISO/IEC and redesignated asISO/IEC 13961:2000)IEEE Standard for Scalable CoherentInterface (SCI)SponsorMicroprocessor and Microcomputer Standards Subcommitteeof theIEEE Computer SocietyApproved 19 March 1992IEEE-SA Stand

2、ards BoardAdopted by ISO/IEC and redesignated asISO/IEC 13961:2000Abstract:The scalable coherent interface (SCI) provides computer-bus-like services but, insteadof a bus, uses a collection of fast point-to-point unidirectional links to provide the far higher through-put needed for high-performance m

3、ultiprocessor systems. SCI supports distributed, sharedmemory with optional cache coherence for tightly coupled systems, and message-passing forloosely coupled systems. Initial SCI links are defined at 1 Gbyte/s (16-bit parallel) and 1 Gb/s(serial). For applications requiring modular packaging, an i

4、nterchangeable module is specifiedalong with connector and power. The packets and protocols that implement transactions aredefined and their formal specification is provided in the form of computer programs. In addition tothe usual read-and-write transactions, SCI supports efficient multiprocessor l

5、ock transactions. Thedistributed cache-coherence protocols are efficient and can recover from an arbitrary number oftransmission failures. SCI protocols ensure forward progress despite multiprocessor conflicts (nodeadlocks or starvation).Keywords:bus architecture, bus standard, cache coherence, dist

6、ributed memory, fiber optic,interconnect,I/O system, link, mesh, multiprocessor, network, packet protocol, ring, seamlessdistributed computer,shared memory, switch, transaction setThe Institute of Electrical and Electronics Engineers, Inc.3 Park Avenue, New York, NY 10016-5997, USACopyright 2001 by

7、the Institute of Electrical and Electronics Engineers, Inc.All rights reserved. Published 23 May 2001. Printed in the United States of America.Print:ISBN 1-55937-222-2 SH15255PDF:ISBN 0-7381-1206-2 SS15255No part of this publication may be reproduced in any form, in an electronic retrieval system or

8、 otherwise, without the prior written permission of the publisher.IEEE Standardsdocuments are developed within the IEEE Societies and the Standards Coordinating Committees of theIEEE Standards Association (IEEE-SA) Standards Board. The IEEE develops its standards through a consensus develop-ment pro

9、cess, approved by the American National Standards Institute, which brings together volunteers representing variedviewpoints and interests to achieve the nal product. Volunteers are not necessarily members of the Institute and serve with-out compensation. While the IEEE administers the process and es

10、tablishes rules to promote fairness in the consensus devel-opment process, the IEEE does not independently evaluate, test, or verify the accuracy of any of the information containedin its standards.Use of an IEEE Standard is wholly voluntary. The IEEE disclaims liability for any personal injury, pro

11、perty or other dam-age, of any nature whatsoever, whether special, indirect, consequential, or compensatory, directly or indirectly resultingfrom the publication, use of, or reliance upon this, or any other IEEE Standard document.The IEEE does not warrant or represent the accuracy or content of the

12、material contained herein, and expressly disclaimsany express or implied warranty, including any implied warranty of merchantability or tness for a specic purpose, or thatthe use of the material contained herein is free from patent infringement. IEEE Standards documents are supplied “AS IS.”The exis

13、tence of an IEEE Standard does not imply that there are no other ways to produce, test, measure, purchase, market,or provide other goods and services related to the scope of the IEEE Standard. Furthermore, the viewpoint expressed at thetime a standard is approved and issued is subject to change brou

14、ght about through developments in the state of the art andcomments received from users of the standard. Every IEEE Standard is subjected to review at least every ve years for revi-sion or reafrmation. When a document is more than ve years old and has not been reafrmed, it is reasonable to concludeth

15、at its contents, although still of some value, do not wholly reect the present state of the art. Users are cautioned to checkto determine that they have the latest edition of any IEEE Standard.In publishing and making this document available, the IEEE is not suggesting or rendering professional or o

16、ther servicesfor, or on behalf of, any person or entity. Nor is the IEEE undertaking to perform any duty owed by any other person orentity to another. Any person utilizing this, and any other IEEE Standards document, should rely upon the advice of a com-petent professional in determining the exercis

17、e of reasonable care in any given circumstances.Interpretations: Occasionally questions may arise regarding the meaning of portions of standards as they relate to specicapplications. When the need for interpretations is brought to the attention of IEEE, the Institute will initiate action to preparea

18、ppropriate responses. Since IEEE Standards represent a consensus of concerned interests, it is important to ensure that anyinterpretation has also received the concurrence of a balance of interests. For this reason, IEEE and the members of its soci-eties and Standards Coordinating Committees are not

19、 able to provide an instant response to interpretation requests except inthose cases where the matter has previously received formal consideration. Comments for revision of IEEE Standards are welcome from any interested party, regardless of membership afliation withIEEE. Suggestions for changes in d

20、ocuments should be in the form of a proposed change of text, together with appropriatesupporting comments. Comments on standards and requests for interpretations should be addressed to:Secretary, IEEE-SA Standards Board445 Hoes LaneP.O. Box 1331Piscataway, NJ 08855-1331USAIEEE is the sole entity tha

21、t may authorize the use of certication marks, trademarks, or other designations to indicate com-pliance with the materials set forth herein.Authorization to photocopy portions of any individual standard for internal or personal use is granted by the Institute ofElectrical and Electronics Engineers,

22、Inc., provided that the appropriate fee is paid to Copyright Clearance Center. Toarrange for payment of licensing fee, please contact Copyright Clearance Center, Customer Service, 222 Rosewood Drive,Danvers, MA 01923 USA; (978) 750-8400. Permission to photocopy portions of any individual standard fo

23、r educationalclassroom use can also be obtained through the Copyright Clearance Center.Note: Attention is called to the possibility that implementation of this standard may require use of subject mat-ter covered by patent rights. By publication of this standard, no position is taken with respect to

24、the existence orvalidity of any patent rights in connection therewith. The IEEE shall not be responsible for identifying patentsfor which a license may be required by an IEEE standard or for conducting inquiries into the legal validity orscope of those patents that are brought to its attention.iiiIn

25、troduction(This introduction is not a part of IEEE Std 1596-1992, IEEE Standard for Scalable Coherent Interface SCI.)The demand for more processing power continues to increase, and apparently has no limit. One can usefully saturatethe resources of any computer so easily by merely specifying a finer

26、mesh or higher resolution for the solution of somephysical problem (hydrodynamics, for example), that engineers and scientists are desperate for enormously largercomputers.To get this kind of computing power, it seems necessary to use a large number of processors cooperatively. Because ofthe propaga

27、tion delays introduced when signals cross chip boundaries, the fastest uniprocessor may be on one chipbefore long. Pipelining and similar large-mainframe tricks are already used extensively on single-chip processors.Vector processors help, but are hard to use efficiently in many applications. Multip

28、rocessors communicating bymessage passing work well for some applications, but not for all. The shared-memory multiprocessor looks like thebest strategy for the future, but a great deal of work will be needed to develop software to use it efficiently.It is important to support both the shared-memory

29、 and the message-passing models efficiently (and at the same time)in order to support optimal software for a wide range of problems, especially for a system that dynamically allocatesprocessors and perhaps changes its configuration depending on the nature of its load.SCI started from an attempt to i

30、ncrease the bandwidth of a backplane bus past the limits set by backplane physics inorder to meet the needs of new generations of processor chips, some of which can single-handedly saturate the fastestbuses. We soon learned that we had to abandon the bus structure to achieve our goals.Backplane perf

31、ormance is limited by physics (distributed capacitances and the speed of light) and by a buss one-at-a-time nature, an inherent bottleneck. To gain performance far beyond what buses and backplanes can do, one needsbetter signaling techniques and the concurrent use of many signaling paths.Rather than

32、 using bused backplane wires, SCI is based on point-to-point interconnect technology. This designapproach eliminates many of the physics problems and results in much higher speeds. SCI in effect simulates a bus,providing the bus services one expects (and more) without using buses.SCI has turned out

33、to be surprisingly simple, much simpler than many of the alternative designs we explored and muchsimpler than bus-based systems would be if they tried to approach a comparable size and performance. This simplicitymay not be obvious to the first-time reader of this rather thick document, but much of

34、this bulk is due to the largeamount of tutorial material necessary to introduce such a new way of doing things (a paradigm shift), and even moreis due to the comprehensive executable description of cache behavior under all possible conditions.The switch from a shared backplane bus to a point-to-poin

35、t interconnect has created many new problems and researchtopics, which have been resolved in record time by this SCI project. Much research remains to be done on determiningoptimal ways to use the mechanisms SCI provides. SCI has also required the development of novel allocation andcache-coherence p

36、rotocols, which has made the project a challenging one indeed, particularly in view of our scheduleobjectives.Historical Perspective and AcknowledgmentsMost of the developers of SCI come from high-speed-bus backgrounds, such as Fastbus (IEEE Std 960-1989) orFuturebus (IEEE Std 896.1-1987). Paul Swea

37、zey, who was the coordinator of the Futurebus cache coherence taskgroup, initiated a SuperBus Study Group under the IEEE Computer Societys Microprocessor Standards Committee inNovember 1987 to consider whether something could be done for the next bus generation to avoid the multitude ofcompeting inc

38、ompatible standards we saw in the 32-bit generation. Futurebus tried to solve that problem, starting inthe late 1970s, but could not converge to a single best solution in time to head off the development of manyalternatives.ivThe SuperBus Study Group met for less than a year before deciding that the

39、re was indeed a way to do better and toachieve the throughput rates that are required for supporting multiple 100-MFLOPS-class processor chips, namelyabout 1 Gbyte/s per processor. We were particularly urged on by Paul L. Borrill, Futurebus chairman, and JohnMoussouris (one of the founders of MIPS),

40、 who frightened us all by his predictions of immensely powerful processorsin the near futurewhich already are coming true!Our July 1988 Project Authorization Request was approved by the IEEE Standards Board in October. David B.Gustavson was appointed Chairman and David V. James became the logical-ta

41、sk-group coordinator and ViceChairman. Gustavson also served as physical-task-group coordinator, handled the records and mailings, and sharedminutes-taking and editing duties with David James.A Control and Status Register and I/O Architecture effort was started within SCI, based on some significantc

42、ontributions by David James. When it was recognized as important for other standard buses as well, it was split off asan independent activity shared by Futurebus+, Serial Bus (P1394), and others. In April 1989 this also became anofficial project, P1212, with David James as chairman. The goal of a un

43、iform CSR architecture has been attemptedmany times before (e.g., by the Fastbus Software Working Group, chaired by Gustavson), and has proven elusive. Thereason P1212 has had a more comprehensive success is that David James brought considerable architecturalexperience to bear, generating sufficient

44、 rationale for the various choices so that decisions no longer seem entirelyarbitrary. Much of this rationale is a consequence of multiprocessor architectural considerations; without the constraintof efficient multiprocessor interoperability, many CSR design issues would be too arbitrary to be able

45、to achieve timelystandardization.The CSR Architecture has become a unifying force for the latest generation of buses, encouraging VME andMULTIBUSII users to use the CSR architecture as they interface to Futurebus+, thus facilitating a future interface toSCI as system requirements grow. In this way,

46、there is a relatively smooth and well-defined growth path from present-generation single-processor systems through Futurebus+s several-processor systems with cache coherence, to SCIsmany-processor systems. Because of the importance of such a migration path to the future acceptance of SCI, we placehi

47、gh priority on interfacing SCI with other buses. For that reason we include protocol hooks that would not otherwisebe needed. In exchange, SCI users will be able to take advantage of the large number of existing I/O interfaces.In March 1989, a Fiber Optic Task Group (SCI-FI) was started, led by Hans

48、 Wiggers, and an SCI/Futurebus+ BridgeTask Group was started, led by Mark Williams (a joint appointment with Futurebus+).Throughout the development of SCI, Knut Alnes and Ernst Kristiansen were working on an early implementation,providing input for the details of the specification. They also initiat

49、ed work at the University of Oslo, by Stein Gjessingand others, on formal verification of the cache-coherence mechanisms. This real implementation effort was extremelyvaluable to SCI, and greatly accelerated convergence to a practical specification.David James generated documents at an incredible rate. As the result of his single-handed effort the bulk of the text ofthis specification first appeared in June 1989. At the same time he was producing two volumes of similar size for theCSR working group! He is convinced that having something on paper produces more productive di