IEEE 1800-2017 en SystemVerilog-Unified Hardware Design Specification and Verification Language (IEEE Computer Society).pdf

1、 IEEE Standard for SystemVerilog Unified Hardware Design, Specification, and Verification Language Sponsored by the Design Automation Standards Committee IEEE 3 Park Avenue New York, NY 10016-5997 USA IEEE Computer Society and the IEEE Standards Association Corporate Advisory Group IEEE Std 1800-201

2、7 (Revision of IEEE Std 1800-2012) IEEE Std 1800-2017(Revision ofIEEE Std 1800-2012)IEEE Standard for SystemVerilogUnified Hardware Design, Specification, and Verification LanguageSponsorDesign Automation Standards Committeeof theIEEE Computer Societyand theIEEE Standards Association Corporate Advis

3、ory GroupApproved 6 December 2017IEEE-SA Standards BoardThe Institute of Electrical and Electronics Engineers, Inc.3 Park Avenue, New York, NY 10016-5997, USACopyright 2018 by The Institute of Electrical and Electronics Engineers, Inc.All rights reserved. Published 21 February 2018. Printed in the U

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32、 infringement of such rights, is entirely theirown responsibility. Further information may be obtained from the IEEE Standards Association.6Copyright 2018 IEEE. All rights reserved.ParticipantsThe SystemVerilog Language Working Group is entity based. At the time this standard was completed,the Syste

33、mVerilog Working Group had the following membership:Karen Pieper, Accellera Systems Initiative, Chair Neil Korpusik, Oracle Corporation, Vice Chair, Technical Chair Dennis Brophy, Mentor, a Siemens Business, SecretaryShalom Bresticker, Accellera Systems Initiative, EditorWork on this standard was di

34、vided among primary committees.The Design and Testbench Committee (SV-BC) was responsible for the specification of the design andtestbench features of SystemVerilog. Matt Maidment, Intel Corporation, Chair Brad Pierce, Synopsys, Inc., Co-Chair The Assertions Committee (SV-AC) was responsible for the

35、 specification of the assertion features ofSystemVerilog. Dmitry Korchemny, Synopsys, Inc., Chair Erik Seligman, Intel Corporation, Co-Chair The Discrete Committee (SV-DC) was responsible for defining features to support modeling of analog/mixed-signal circuit components in the discrete domain. Scot

36、t Little, Mentor, a Siemens Business, Chair Scott Cranston, Cadence Design Systems, Inc., Co-Chair Dave Rich, Mentor, a Siemens BusinessDmitry Korchemny, Synopsys, Inc.Michiel Ligthart, Design Automation, Inc.Matt Maidment, Intel CorporationScott Little, Mentor, a Siemens BusinessCharles Dawson, Cad

37、ence Design Systems, Inc.Shalom Bresticker, Accellera Systems InitiativeJonathan Bromley, Oracle CorporationEric Coffin, Mentor, a Siemens BusinessMark Hartoog, Synopsys, Inc.Neil Korpusik, Oracle CorporationFrancoise Martinolle, Cadence Design Systems, Inc.C. Venkat Ramana Rao, Mentor, a Siemens Bu

38、sinessJustin Refice, NVIDIA CorporationDave Rich, Mentor, a Siemens BusinessRay Ryan, Mentor, a Siemens BusinessArturo Salz, Synopsys, Inc.Steven Sharp, Cadence Design Systems, Inc.Mark Strickland, Cisco Systems, Inc.Brandon Tipp, Intel CorporationMehbub Ali, Intel CorporationShalom Bresticker, Acce

39、llera Systems InitiativeEduard Cerny, Synopsys, Inc.Ang Boon Chong, Intel CorporationBen Cohen, Accellera Systems InitiativeManisha Kulshrestha, Mentor Graphics CorporationAnupam Prabhakar, Mentor Graphics CorporationSamik Sengupta, Synopsys, Inc.Kevin Cameron, SamsungShekar Chetput, Cadence Design

40、Systems, Inc.Dave Cronauer, Synopsys, Inc.Mark Hartoog, Synopsys, Inc.Arturo Salz, Synopsys, Inc.Aaron Spratt, Cadence Design Systems, Inc.Martin Vlach, Mentor, a Siemens BusinessGordon Vreugdenhil, Mentor, a Siemens Business7Copyright 2018 IEEE. All rights reserved.The following members of the enti

41、ty balloting committee voted on this standard. Balloters may have votedfor approval, disapproval, or abstention. When the IEEE-SA Standards Board approved this standard on 6 December 2017, it had the followingmembership:Jean-Philippe Faure, ChairGary Hoffman, Vice ChairJohn D. Kulick, Past ChairKons

42、tantinos Karachalios, Secretary*Member EmeritusAccellera Systems Initiative, Inc.Cadence Design Systems, Inc.Cisco Systems, Inc.Intel CorporationOracle, Inc.Siemens CorporationSynopsys, Inc.Verific Design Automation, Inc.Chuck AdamsMasayuki AriyoshiTed BurseStephen DukesDoug EdwardsJ. Travis Griffit

43、hMichael JanezicThomas KoshyJoseph L. Koepfinger*Kevin LuDaleep MohlaDamir NovoselRonald C. PetersenAnnette D. ReillyRobby RobsonDorothy StanleyAdrian StephensMehmet UlemaPhil WennblomHoward WolfmanYu Yuan8Copyright 2018 IEEE. All rights reserved.IntroductionThe purpose of this standard is to provid

44、e the electronic design automation (EDA), semiconductor, andsystem design communities with a well-defined and official IEEE unified hardware design, specification,and verification standard language. The language is designed to coexist and enhance the hardwaredescription and verification languages (H

45、DVLs) presently used by designers while providing the capabilitieslacking in those languages. SystemVerilog is a unified hardware design, specification, and verification language based on the AccelleraSystemVerilog 3.1a extensions to the Verilog hardware description language (HDL) B4, published in20

46、04. Accellera is a consortium of EDA, semiconductor, and system companies. IEEE Std1800 enables aproductivity boost in design and validation and covers design, simulation, validation, and formalassertion-based verification flows. SystemVerilog enables the use of a unified language for abstract and d

47、etailed specification of the design,specification of assertions, coverage, and testbench verification based on manual or automaticmethodologies. SystemVerilog offers application programming interfaces (APIs) for coverage andassertions, and a direct programming interface (DPI) to access proprietary f

48、unctionality. SystemVerilogoffers methods that allow designers to continue to use present design languages when necessary to leverageexisting designs and intellectual property (IP). This standardization project will provide the VLSI designengineers with a well-defined IEEE standard, which meets thei

49、r requirements in design and validation, andwhich enables a step function increase in their productivity. This standardization project will also providethe EDA industry with a standard to which they can adhere and that they can support in order to deliver theirsolutions in this area.This introduction is not part of IEEE Std 1800-2017, IEEE Standard for SystemVerilogUnified Hardware Design,Specification, and Verification Language.9Copyright 2018 IEEE. All rights reserved.ContentsPart One: Design and Verification Constructs1. Overview.381.1 Scope381.2 Purpose.381.3 Cont