ISO IEC 15776-2001 VME64bus - Specification《VME64总线 规范》.pdf

1、INTERNATIONAL STANDARD ISO/IEC 15776 First edition 2001-12 VME64bus Specification Reference number ISO/IEC 15776:2001(E)INTERNATIONAL STANDARD ISO/IEC 15776 First edition 2001-12 VME64bus Specification PRICE CODE ISO/IEC 2001 All rights reserved. Unless otherwise specified, no part of this publicati

2、on may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying and microfilm, without permission in writing from the publisher. ISO/IEC Copyright Office Case postale 56 CH-1211 Genve 20 Switzerland XF For price, see current catalogue 2 15776 ISO/IEC:20

3、01(E) CONTENTS FOREWORD 8 INTRODUCTION9 1 General13 1.1 Scope and object 13 1.2 Normative references13 1.3 VMEbus interface system elements14 1.4 VMEbus specification diagrams20 1.5 Specification terminology 22 1.6 Protocol specification 24 1.7 System examples and explanations25 2 Data transfer bus.

4、25 2.1 Introduction25 2.2 Data-transfer-bus lines27 2.3 DTB modules Basic description .38 2.4 Typical operation.64 2.5 Data-transfer-bus acquisition 73 2.6 DTB timing rules and observations .75 3 Data transfer bus arbitration120 3.1 Bus arbitration philosophy.120 3.2 Arbitration bus lines.122 3.3 Fu

5、nctional modules .124 3.4 Typical operation.132 3.5 Race conditions between master requests and arbiter grants141 4 Priority interrupt bus.141 4.1 Introduction141 4.2 Priority interrupt bus lines144 4.3 Priority interrupt bus modules Basic description 146 4.4 Typical operation.159 4.5 Race condition

6、s.165 4.6 Priority interrupt bus timing rules and observations 166 5 Utility bus .183 5.1 Introduction183 5.2 Utility bus signal lines. .183 5.3 Utility bus modules 183 5.4 System initialization and diagnostics.186 5.5 Power and ground pins .190 5.6 Reserved line 191 5.7 Auto slot ID191 5.8 Auto sys

7、tem controller.198 6 Electrical specifications .199 6.1 Introduction199 6.2 Power distribution200 6.3 Electrical signal characteristics .201 6.4 Bus driving and receiving requirements 20215776 ISO/IEC:2001(E) 3 6.5 Backplane signal line interconnections .206 6.6 User defined signals210 6.7 Signal li

8、ne drivers and terminations 210 7 Mechanical specifications212 7.1 Introduction212 7.2 VMEbus boards.213 7.3 Front panels 217 7.4 Backplanes220 7.5 Assembly of VMEbus subracks.222 7.6 Conduction cooled VMEbus systems223 7.7 VMEbus backplane connectors and VMEbus board connectors 223 Annex A (normati

9、ve) Glossary of VMEbus terms 245 Annex B (normative) VMEbus Connector/Pin description .251 Annex C (normative) Manufacturers board identification255 Rule index.257 Figure 1 System elements. 15 Figure 2 Functional modules and buses 21 Figure 3 Signal timing notation 25 Figure 4 Data transfer bus func

10、tional block diagram .28 Figure 5 Block diagram Master .39 Figure 6 Block diagram Slave. 41 Figure 7 Block diagram Bus timer . .43 Figure 8 Block diagram Location monitor .44 Figure 9 Four ways in which 32 bits of data might be stored in memory.53 Figure 10 Four ways in which 16 bits of data might b

11、e stored in memory.54 Figure 11 Block diagram Configuration ROM / Control & Status registers.59 Figure 12 Example of a non-multiplexed address, single-byte read cycle 66 Figure 13 Example of multiplexed address double-byte write cycle67 Figure 14 Example of non-multiplexed address quad-byte write cy

12、cle69 Figure 15 Example of an eight-byte block read cycle 70 Figure 16 Data transfer bus master exchange sequence .74 Figure 17 Address broadcast timing All cycles .94 Figure 18 A16, A24, A32 master, responding slave, and location monitor95 Figure 19 Master, slave, and location monitor A16, A24 and

13、A32 address broadcast timing 96 Figure 20 Master, slave, and location monitor A16, A24, and A32 address broadcast timing 97 Figure 21 Master, slave and location monitor A64, A40, and ADOH address broadcast timing .98 Figure 22 Master, slave, and location monitor data transfer timing.99 Figure 23 Mas

14、ter, slave, and location monitor data transfer timing.101 4 15776 ISO/IEC:2001(E) Figure 24 Master, slave and location monitor data transfer timing A40 multiplexed quad byte read, A40BLT multiplexed quad byte block read, MBLT eight byte block read .103 Figure 25 Master, slave and location monitor da

15、ta transfer timing105 Figure 26 Master, slave and location monitor data transfer timing107 Figure 27 Master, slave and location monitor data transfer timing A40 multiplexed quad byte write, A40BLT multiplexed quad byte block write, MBLT eight byte block write 109 Figure 28 Master, slave and location

16、 monitor data transfer timing single-byte RMW cycles 111 Figure 29 Master, slave and location monitor data transfer timing double-byte RMW cycles, quad-byte RMW cycles.112 Figure 30 Address strobe inter-cycle timing 113 Figure 31 Data strobe inter-cycle timing. .113 Figure 32 Data strobe inter-cycle

17、 timing. .114 Figure 33 Master, slave and bus timer data transfer timing timed-out cycle .114 Figure 34 Master DTB control transfer timing. .115 Figure 35 Master and slave data transfer timing master responding to RETRY* line .116 Figure 36 Master and slave data transfer timing master ignoring RETRY

18、 line 117 Figure 37 A40, MD32 read-modify-write 118 Figure 38 Rescinding DTACK timing .119 Figure 39 Arbitration functional block diagram . .121 Figure 40 Illustration of the daisy chain bus grant lines .123 Figure 41 Block diagram Arbiter .127 Figure 42 Block diagram Requester .130 Figure 43 Arbit

19、ration flow diagram two requesters, two request levels .134 Figure 44 Arbitration sequence diagram two requesters, two request levels 136 Figure 45 Arbitration flow diagram two requesters, same request level137 Figure 46 Arbitration sequence diagram two requesters, same request level.140 Figure 47 P

20、riority interrupt bus functional diagram 142 Figure 48 Interrupt subsystem structure Single handler system 143 Figure 49 Interrupt subsystem structure Distributed system 144 Figure 50 IACKIN*/IACKOUT* DAISY-CHAIN.146 Figure 51 Block diagram Interrupt handler .148 Figure 52 Block diagram Interrupter

21、151 Figure 53 Block diagram IACK daisy-chain driver 15 2 Figure 54 Release of interrupt request lines by ROAK and RORA interrupters 156 Figure 55 IACK daisy-chain driver and interrupter on the same board158 Figure 56 Two interrupters on the same board . 159 Figure 57 The three phases of an interrup

22、t sequence.160 Figure 58 Two interrupt handlers, each monitoring one interrupt request line 161 Figure 59 Two interrupt handlers, each monitoring several interrupt request lines.16215776 ISO/IEC:2001(E) 5 Figure 60 Typical single handler interrupt system operation flow diagram164 Figure 61 Typical d

23、istributed interrupt system with two interrupt handlers, flow diagram165 Figure 62 Interrupt handler and interrupter Interrupter selection timing single-byte, double-byte and quad-byte interrupt acknowledge cycles 178 Figure 63 IACK daisy-chain driver Interrupter selection timing single-byte, double

24、byte, and quad-byte interrupt acknowledge cycles178 Figure 64 Participating interrupter Interrupter selection timing single-byte, double-byte, and quad-byte interrupt acknowledge cycles179 Figure 65 Responding interrupter Interrupter selection timing single-byte, double-byte, and quad-byte interrup

25、t acknowledge cycles179 Figure 66 Interrupt handler Status/ID transfer timing single-byte interrupt acknowledge cycle180 Figure 67 Interrupt handler Status/ID transfer timing double-byte and quad-byte interrupt acknowledge cycles180 Figure 68 Responding interrupter Status/ID transfer timing single-b

26、yte interrupt acknowledge cycle181 Figure 69 Responding interrupter Status/ID transfer timing double-byte interrupt acknowledge cycle quad-byte interrupt acknowledge cycle .182 Figure 70 IACK daisy-chain driver, responding interrupter and participating interrupter IACK daisy-chain inter-cycle timing

27、 182 Figure 71 Utility bus block diagram 184 Figure 72 System clock driver timing. 185 Figure 73 Block diagram of power monitor module.186 Figure 74 Power monitor power failure timing . 187 Figure 75 Power monitor system restart timing .187 Figure 76 SYSRESET* and SYSFAIL* timing diagram .190 Figure

28、 77 Current rating for power pins .191 Figure 78 CR/CSR auto ID slave initialization algorithm .195 Figure 79 First slot detector (FSD) 198 Figure 80 VMEbus signal levels . .201 Figure 81 Standard bus termination . .208 Figure 82 Subrack with mixed board sizes. .226 Figure 83 Single height board Bas

29、ic dimensions2 27 Figure 84 Double height board Basic dimensions 228 Figure 85 Connector positions on single and double height boards229 Figure 86 Cross-sectional view of board, connector, backplane, and front panel.230 Figure 87 Optional enhanced DIN connector 231 Figure 88 Component height, lead l

30、ength and board warpage232 Figure 89 Single height, single width front panel .233 Figure 90 Double height, single width front panel 234 Figure 91 Front panel mounting brackets and dimension of single height boards. .235 Figure 92 Front panel mounting brackets and dimension of double height boards.23

31、6 Figure 93 Single height filler panel . .237 6 15776 ISO/IEC:2001(E) Figure 94 Double height filler panel . 238 Figure 95 Backplane detailed dimensions of a J1 and a J2 backplane.239 Figure 96 Detailed dimensions of a J1/J2 backplane240 Figure 97 “Off-board type“ backplane terminations (viewed from

32、 top of backplane) 241 Figure 98 “On-board type“ backplane terminations (viewed from top of backplane).242 Figure 99 21 slot subrack 243 Figure 100 Board guide detail 244 Table 1 The eight categories of byte locations . .29 Table 2 Address alignment on bus . .29 Table 3 Signal levels during data tra

33、nsfers used to select which byte location(s) are accessed during a data transfer .31 Table 4 Address modifier codes. .33 Table 5 Use of data lines to move data during nonmultiplexed data transfers35 Table 6 Use of the address and data lines for multiplexed data cycles.36 Table 7 RULEs and PERMISSION

34、s specifying the use of the dotted lines by the various types of masters.40 Table 8 Slaves RULEs and PERMISSIONs specifying the use of the dotted lines by the various type of slaves.42 Table 9 Use of the BTO( ) mnemonic specifying the time-out period of bus timers43 Table 10 Location monitors RULEs

35、and PERMISSIONs specifying the use of the dotted lines by the various types of location monitors 45 Table 11 Mnemonics specifying addressing capabilities.46 Table 12 Mnemonics specifying basic data transfer capabilities.48 Table 13 Mnemonics specifying block transfer capabilities.51 Table 14 The mne

36、monic that specifies read-modify-write capabilities 52 Table 15 Transferring 32 bits of data using multiple-byte transfer cycles .54 Table 16 Transferring 16 bits of data using multiple-byte transfer cycles .55 Table 17 Mnemonic that specifies unaligned transfer capability .55 Table 18 Mnemonics spe

37、cifying address only capability.56 Table 19 Configuration ROM/control & status registers: RULEs and PERMISSIONs or monitoring the dashed lines60 Table 20 Control and status register base definition . 60 Table 21 Configuration ROM definition 61 Table 22 Timing diagrams defining master, slave, and loc

38、ation monitor operation (see Table 27 for timing values) .76 Table 23 Definitions of mnemonics used in Tables 24, 25 and 2678 Table 24 Use of the address and data lines to select a byte group.78 Table 25 Use of DS1*, DS0*, A1, A2, and LWORD* during the address phase of the various cycles79 Table 26

39、Use of the data lines to transfer data 8015776 ISO/IEC:2001(E) 7 Table 27 Master, slave, and location monitor timing parameters83 Table 28 Bus-timer timing parameters (see also Table 32) 84 Table 29 Master, timing RULEs and OBSERVATIONs.84 Table 30 Slave, timing RULEs and OBSERVATIONs.89 Table 31 Lo

40、cation monitor, timing OBSERVATIONs.93 Table 32 BUS TIMER, timing RULEs . .94 Table 33 RULEs and PERMISSIONs specifying the use of the dotted lines by the various types of arbiters 128 Table 34 RULEs and PERMISSIONs specifying the use of the dotted lines by the various types of requesters .131 Table

41、 35 RULEs and PERMISSIONs specifying the use of the dotted lines in Figure 51 by the various types of interrupt handlers149 Table 36 RULEs and PERMISSIONs specifying the use of the dotted lines in Figure 52 by the various types of interrupters .151 Table 37 Use of the IH( ) mnemonic to specify inter

42、rupt request handling capabilities.153 Table 38 Use of the I( ) mnemonic to specify interrupt request generation capabilities153 Table 39 Mnemonics specifying status/ID transfer capabilities.153 Table 40 Mnemonics specifying interrupt request release capabilities .155 Table 41 3-bit interrupt acknow

43、ledge code 164 Table 42 Timing diagrams defining interrupt handler and interrupter operation167 Table 43 Timing diagrams defining IACK daisy-chain driver operation.168 Table 44 Timing diagrams defining participating interrupter operation168 Table 45 Timing diagrams that define responding interrupter

44、 operation.168 Table 46 Definitions of mnemonics used in tables 47, 48 and 49 .169 Table 47 Use of addressing lines during interrupt acknowledge cycles 169 Table 48 Use of the DS1*, DS0*, LWORD* and WRITE* lines during iterrupt acknowledge cycles170 Table 49 Use of the data bus lines to transfer the

45、 Status/ID.170 Table 50 Interrupt handler, interrupter and IACK daisy-chain driver timing parameters .171 Table 51 Interrupt handler, timing RULEs and OBSERVATIONs .172 Table 52 Interrupter, timing RULEs and OBSERVATIONs .174 Table 53 IACK daisy-chain driver, timing RULEs and OBSERVATIONs 177 Table

46、54 Module drive during power-up and power-down sequences 189 Table 55 Bus voltage specification . .200 Table 56 Bus driving and receiving requirements .2 02 Table 57 Bus driver summary 211 Table 58 J1/P1 pin assignments . 224 Table 59 J2/P2 pin assignments . 225 8 15776 ISO/IEC:2001(E) VME64bus SPEC

47、IFICATION FOREWORD 1) ISO (the International Organization for Standardization) and IEC (the International Electrotechnical Commission) form the specialized system for worldwide standardization. National bodies that are members of ISO or IEC participate in the development of International Standards t

48、hrough technical committees established by the respective organization to deal with particular fields of technical activity. ISO and IEC technical committees collaborate in fields of mutual interest. Other international organizations, governmental and non-governmental, in liaison with ISO and IEC, also take part in the work. 2) In the field of information technology, ISO and IEC have established a joint technical committee, ISO/IEC JTC1. Draft International Standard