A Parameterized Floating Point Library Applied to .ppt

1、A Parameterized Floating Point Library Applied to Multispectral Image Clustering,Xiaojun Wang Dr. Miriam Leeser Rapid Prototyping Laboratory Northeastern University,Wang,P166/MAPLD 2004,2,Outline,Project overview Library hardware modules Floating point divider and square root K-means clustering appl

2、ication for multispectral satellite images using the floating point library Conclusions and future work,Wang,P166/MAPLD 2004,3,Variable Precision Floating Point Library,A library of fully pipelined and parameterized floating point modulesImplementations well suited for state of the art FPGAs Xilinx

3、Virtex II FPGAs and Altera Stratix devices Embedded Multipliers and Block RAMSignal/image processing algorithms accelerated using this library,Wang,P166/MAPLD 2004,4,Questions to Answer,Why floating point (FP)?Why parameterized FP?Why FPGAs?,Wang,P166/MAPLD 2004,5,Why Floating Point (FP) ?,Fixed Poi

4、ntLimited range Number of bits grows for more accurate results Easy to implement in hardware,Floating PointDynamic range Accurate results More complex and higher cost to implement in hardware,Wang,P166/MAPLD 2004,6,Floating Point Representation,(-1)s * 1.f * 2e-BIAS,Wang,P166/MAPLD 2004,7,Why Parame

5、terized FP ?,Minimize the bitwidth of each signal in the datapath Make more parallel implementations possible Reduce the power dissipationFurther acceleration Custom datapaths built in reconfigurable hardware using either fixed-point or floating point arithmetic Hybrid representations supported thro

6、ugh fixed-to-float and float-to-fixed conversions,Wang,P166/MAPLD 2004,8,Why FPGA ?,Flexible FPGA architecture LUTs, BlockRAM or SRL16 Embedded multiplier, embedded power PCCustomize design architecture to suit algorithm parallel, serial, bitwidthFine grained parallelism high computational workloadA

7、llow cost / performance tradeoffs Small area, low latency, high throughput, low power dissipationFaster than general purpose processor, more flexible and lower cost than ASICHigh Performance Signal Processing Easy and Affordable in FPGAs,Wang,P166/MAPLD 2004,9,Outline,Project overview Library hardwa

8、re modules Floating point divider and square root K-means clustering application for multispectral satellite images using the floating point library Conclusions and future work,Wang,P166/MAPLD 2004,10,Parameterized FP Modules,Arithmetic operation fp_add : floating point addition fp_sub : floating po

9、int subtraction fp_mul : floating point multiplication fp_div : floating point division fp_sqrt : floating point square rootFormat control denorm : introducing implied integer digit rnd_norm : rounding and normalizingFormat conversion fix2float : converting from fixed point to floating point float2f

10、ix : converting from floating point to fixed point,Wang,P166/MAPLD 2004,11,What Makes Our Library Unique ?,A superset of all floating point formats including IEEE standard formatParameterized for variable precision arithmetic Support custom floating point datapaths Support hybrid fixed and floating

11、point implementations Support fully pipelining Synchronization signals Complete Separate normalization Rounding (“round to zero” and “round to nearest”) Some error handling,Wang,P166/MAPLD 2004,12,Generic Library Component,Synchronization signals for pipelining READY and DONESome error handling feat

12、ures EXCEPTION_IN and EXCEPTION_OUT,Wang,P166/MAPLD 2004,13,One Example - Assembly of Modules,2 denorm + 1 fp_add + 1 rnd_norm = 1 IEEE single precision adder,Wang,P166/MAPLD 2004,14,Another Example - Floating Point Multiplier,Wang,P166/MAPLD 2004,15,Latency,Clock rate of each module is similar,Wang

13、,P166/MAPLD 2004,16,Outline,Project overview Library hardware modules Floating point divider and square root K-means clustering application for multispectral satellite images using the library Conclusions and future work,Wang,P166/MAPLD 2004,17,Algorithms for Division and Square Root,Division P. Hun

14、g, H. Fahmy, O. Mencer, and M. J. Flynn, “Fast division algorithm with a small lookup table,“ Asilomar Conference,1999Square Root M. D. Ercegovac, T. Lang, J.-M. Muller, and A. Tisserand, “Reciprocation, square root, inverse square root, and some elementary functions using small multipliers,“ IEEE T

15、ransactions on Computers, vol. 2, pp. 628-637, 2000,Wang,P166/MAPLD 2004,18,Why Choose These Algorithms?,Both algorithms are simple and elegant Based on Taylor series Use small table-lookup method with small multipliersVery well suited to FPGA implementations BlockRAM, distributed memory, embedded m

16、ultiplier Lead to a good tradeoff of area and latencyCan be fully pipelined Clock speed similar to all other components,Wang,P166/MAPLD 2004,19,Division Algorithm,Wang,P166/MAPLD 2004,20,Division Algorithm Continue,Wang,P166/MAPLD 2004,21,Division Data Flow,Wang,P166/MAPLD 2004,22,Square Root Data F

17、low,Reduce the input Y to a very small number A,Compute first terms of Taylor series,Wang,P166/MAPLD 2004,23,Square Root Reduction,Wang,P166/MAPLD 2004,24,Square Root - Evaluation,Wang,P166/MAPLD 2004,25,Our Experiments,Designs specified in VHDLMapped to Xilinx Virtex II FPGA (XC2V3000) System clock

18、 rates up to 300 MHz Density up to 8M system gates 14,336 slices 96 18x18 Embedded Multipliers 96 18Kb BlockRAM (1,728 Kb) 448 Kb Distributed MemoryCurrently targeting Annapolis Wildcard-II,Wang,P166/MAPLD 2004,26,Results - FP Divider on XC2V3000,The last column is the IEEE single precision floating

19、 point format,Wang,P166/MAPLD 2004,27,Results - FP Square Root on XC2V3000,Wang,P166/MAPLD 2004,28,Outline,Project overview Library hardware modules Floating point divider and square root K-means clustering application for multi-spectral satellite images using the library Conclusions and future work

20、,Wang,P166/MAPLD 2004,29,Application : K-means Clustering for Multispectral Satellite Images,Wang,P166/MAPLD 2004,30,K-means Iterative Algorithm,Each cluster has a center (mean value) Initialized on host Initialization done once for complete image processing Cluster assignment Distance (Manhattan no

21、rm) of each pixel and cluster center Accumulation of pixel value of each cluster Mean update via dividing the accumulator value by number of pixels (done once per iteration) Previously done on host Moved to FPGA with fp_div,Wang,P166/MAPLD 2004,31,K-means Clustering Functional Units,Subtraction,Addi

22、tion,Comparison,DATAPATH,Abs. Value,Pixel Data,Validity,Cluster Centers,Memory Acknowledge,Data Valid,Datapath,Pixel Shift,Accumulators,Cluster Assignment,Mean Update Division,Pixel Data,Wang,P166/MAPLD 2004,32,Outline,Project overview Library hardware modules Floating point divider and square root

23、K-means clustering application for multispectral satellite images using the library Conclusions and future work,Wang,P166/MAPLD 2004,33,Conclusion,A Library of fully pipelined and parameterized hardware modules for floating point arithmeticFlexibility in forming custom floating point formatsNew modu

24、le fp_div and fp_sqrt have small area and low latency, are easily pipelinedK-means clustering algorithm applied to multispectral satellite images makes use of fp_div,Wang,P166/MAPLD 2004,34,Future Work,More applications using fp_div and fp_sqrtNew library modules ACC, MAC, INV_SQRTUse floating point lib to implement floating point coprocessor on FPGA with embedded processor,