Dynamically Reconfigurable Architectures- An Overview.ppt

1、Dynamically Reconfigurable Architectures: An Overview,Juanjo Noguera Dept. Computer Architecture (DAC-UPC) jnogueraac.upc.es,2,Introduction Reconfigurable Computing Reconfigurable devices and systems Reconfigurable Systems Classification Reconfiguration Methods Reconfigurable Instruction Set Process

2、ors ASIP-based approach Coprocessor-based approach Conclusions,Outline,3,Reconfigurable Computing (RC) is an emerging paradigm for digital systems designTechnology improvements have made possible new programmable logic devices (FPGAs, CPLDs)Objective of the talk: Give an overview of RC concepts and

3、introduce the Reconfigurable Instruction Set Processors.,Introduction,4,Introduction (II),RC objectives: Specialization, performance, flexibilityBasic idea: “Programmable Hardware”,5,Introduction (III),RC comparison versus other alternatives,6,Introduction Reconfigurable Computing Reconfigurable dev

4、ices and systems Reconfigurable Systems Classification Reconfiguration Methods Reconfigurable Instruction Set Processors ASIP-based approach Coprocessor-based approach Conclusions,Outline,7,General device architecture,Reconfigurable Devices,Reconfigurable Computing,8,Routing strategies,Reconfigurabl

5、e Devices (II),Reconfigurable Computing,9,SRAM based devices with infinite number of reconfigurations,Reconfigurable Devices (III),Reconfigurable Computing,Configuration Bitstream 110011101 .,Reconfigurable Device,10,Rapid System (ASIC) Prototyping,Reconfigurable Systems (I),Reconfigurable Computing

6、PLD,PLD,PLD,CPU,PLD,11,Reconfigurable Systems Classification,Reconfigurable Systems (II),Reconfigurable Computing,I/O,PLD,RAM,PLD,CPU,RAM,PLD,PLD,RAM,(c),(d),(b),(a),Host Computer,SYSTEM BUS,12,Reconfiguration Methods (I),Reconfigurable Computing,Compile Time Reconfiguration (CTR) Device configurat

7、ion is fixed during application run time executionRun Time Reconfiguration (RTR) Device configuration changes during application run time executionRTR strategies Global RTR Partial RTR,13,Global Run Time Reconfiguration (Single context),Reconfiguration Methods (II),Reconfigurable Computing,#1,#2,#3,

8、4,Application,#1,Reconfiguration Contexts,Dynamically Reconfigurable Device,Reconfiguration,14,Partial Run Time Reconfiguration (Multiple context),Reconfiguration Methods (III),Reconfigurable Computing,#1,#2,#3,#4,Aplicaci,Reconfiguration Contexts,Dynamically Reconfigurable Device,#4,#1,#3,15,Run-T

9、ime Reconfiguration Challenges Temporal Partitioning Context Scheduling (static)Reconfiguration Latency Overhead Configuration Pre-fetching Configuration Caching Configuration Compression,Reconfiguration Methods (IV),Reconfigurable Computing,16,Introduction Reconfigurable Computing Reconfigurable de

10、vices and systems Reconfigurable Systems Classification Reconfiguration Methods Reconfigurable Instruction Set Processors ASIP-based approach Coprocessor-based approach Conclusions,Outline,17,By including reconfigurability we can increase flexibility with high specialization,Introduction,Reconfigura

11、ble Instruction Set Processors,Processor,PLD,Reconfigurable Processor,18,Coprocessor based approachASIP based approach,Introduction (II),Reconfigurable Instruction Set Processors,19,Typical example: CPU + PCI board Altera ARC-PCI Compaq PametteSystem on Chip (SoC) Alteras Excalibur device Chameleon

12、Systems, Inc.,Coprocessor based approach (I),Reconfigurable Instruction Set Processors,20,Altera ARC-PCI,Coprocessor based approach (II),Reconfigurable Instruction Set Processors,21,Compaq Pamette,Coprocessor based approach (III),Reconfigurable Instruction Set Processors,22,Alteras Excalibur device

13、Embedded Processor: ARM, MIPS or NIOS,Coprocessor based approach (IV),Reconfigurable Instruction Set Processors,23,Chameleon Systems, Inc.,Coprocessor based approach (V),Reconfigurable Instruction Set Processors,24,Reconfigurable unit within CPU,ASIP based approach (I),Reconfigurable Instruction Set

14、 Processors,25,Challenge: CAD tools,ASIP based approach (II),Reconfigurable Instruction Set Processors,26,ASIP based approach (III),Reconfigurable Instruction Set Processors,27,Example: Philips CinCISe Architecture,ASIP based approach (II),Reconfigurable Instruction Set Processors,28,Application exa

15、mple: DES & A5 encryptation algorithms,ASIP based approach (III),Reconfigurable Instruction Set Processors,srl $13, $2, 20 andi $25, $13, 1 srl $14, $2, 21 andi $24, $14, 6 or $15, $25, $24 srl $13, $2, 22 andi $14, $13, 56 or $25, $15, $14 sll $24, $25, 2,srl $24, $5, 18 srl $25, $5, 17 xor $8, $24

16、 $25 srl $9, $5, 16 xor $10, $8, $9 srl $11, $5, 13 xor $12, $10, $11 andi $13, $12, 1,29,Reconfigurable Computing is an emerging and interesting computing paradigmRC devices and architectures are becoming a realityThere is a big challenge is High-level synthesis (CAD) tools,Conclusions,30,What is the future ?,Conclusions (II),Flexibility, Power,Performance,GPP,RC,RC,