Introduction toCMOS VLSIDesignLayout, Fabrication, and .ppt

1、Introduction to CMOS VLSI Design Layout, Fabrication, and Elementary Logic Design,Fabrication and Layout,Slide 2,Introduction,Integrated circuits: many transistors on one chip. Very Large Scale Integration (VLSI): very many Metal Oxide Semiconductor (MOS) transistor Fast, cheap, low-power transistor

2、s Complementary: mixture of n- and p-type leads to less power Today: How to build your own simple CMOS chip CMOS transistors Building logic gates from transistors Transistor layout and fabrication Rest of the course: How to build a good CMOS chip,Fabrication and Layout,Slide 3,Silicon Lattice,Transi

3、stors are built on a silicon substrate Silicon is a Group IV material Forms crystal lattice with bonds to four neighbors,Fabrication and Layout,Slide 4,Dopants,Silicon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity Group V: extra el

4、ectron (n-type) Group III: missing electron, called hole (p-type),Fabrication and Layout,Slide 5,p-n Junctions,A junction between p-type and n-type semiconductor forms a diode. Current flows only in one direction,Fabrication and Layout,Slide 6,nMOS Transistor,Four terminals: gate, source, drain, bod

5、y Gate oxide body stack looks like a capacitor Gate and body are conductors SiO2 (oxide) is a very good insulator Called metal oxide semiconductor (MOS) capacitor Even though gate is no longer made of metal,Fabrication and Layout,Slide 7,nMOS Operation,Body is commonly tied to ground (0 V) When the

6、gate is at a low voltage: P-type body is at low voltage Source-body and drain-body diodes are OFF No current flows, transistor is OFF,Fabrication and Layout,Slide 8,nMOS Operation,When the gate is at a high voltage: Positive charge on gate of MOS capacitor Negative charge attracted to body Inverts a

7、 channel under gate to n-type Now current can flow through n-type silicon from source through channel to drain, transistor is ON,Fabrication and Layout,Slide 9,pMOS Transistor,Similar, but doping and voltages reversed Body tied to high voltage (VDD) Gate low: transistor ON Gate high: transistor OFF

8、Bubble indicates inverted behavior,Fabrication and Layout,Slide 10,Power Supply Voltage,GND = 0 V In 1980s, VDD = 5V VDD has decreased in modern processes High VDD would damage modern tiny transistors Lower VDD saves power VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, ,Fabrication and Layout,Slide 11,Transist

9、ors as Switches,We can view MOS transistors as electrically controlled switches Voltage at gate controls path from source to drain,Fabrication and Layout,Slide 12,CMOS Inverter,Fabrication and Layout,Slide 13,CMOS Inverter,Fabrication and Layout,Slide 14,CMOS Inverter,Fabrication and Layout,Slide 15

10、,CMOS NAND Gate,Fabrication and Layout,Slide 16,CMOS NAND Gate,Fabrication and Layout,Slide 17,CMOS NAND Gate,Fabrication and Layout,Slide 18,CMOS NAND Gate,Fabrication and Layout,Slide 19,CMOS NAND Gate,Fabrication and Layout,Slide 20,CMOS NOR Gate,Fabrication and Layout,Slide 21,3-input NAND Gate,

11、Y pulls low if ALL inputs are 1 Y pulls high if ANY input is 0,Fabrication and Layout,Slide 22,3-input NAND Gate,Y pulls low if ALL inputs are 1 Y pulls high if ANY input is 0,Fabrication and Layout,Slide 23,CMOS Fabrication,CMOS transistors are fabricated on silicon wafer Lithography process simila

12、r to printing press On each step, different materials are deposited or etched Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process,Fabrication and Layout,Slide 24,Inverter Cross-section,Typically use p-type substrate for nMOS transistor Requires

13、n-well for body of pMOS transistors Several alternatives: SOI, twin-tub, etc.,Fabrication and Layout,Slide 25,Well and Substrate Taps,Substrate must be tied to GND and n-well to VDD Metal to lightly-doped semiconductor forms poor connection called Shottky Diode Use heavily doped well and substrate c

14、ontacts / taps,Fabrication and Layout,Slide 26,Inverter Mask Set,Transistors and wires are defined by masks Cross-section taken along dashed line,Fabrication and Layout,Slide 27,Detailed Mask Views,Six masks n-well Polysilicon n+ diffusion p+ diffusion Contact Metal,Fabrication and Layout,Slide 28,F

15、abrication Steps,Start with blank wafer Build inverter from the bottom up First step will be to form the n-well Cover wafer with protective layer of SiO2 (oxide) Remove layer where n-well should be built Implant or diffuse n dopants into exposed wafer Strip off SiO2,Fabrication and Layout,Slide 29,O

16、xidation,Grow SiO2 on top of Si wafer 900 1200 C with H2O or O2 in oxidation furnace,Fabrication and Layout,Slide 30,Photoresist,Spin on photoresist Photoresist is a light-sensitive organic polymer Softens where exposed to light,Fabrication and Layout,Slide 31,Lithography,Expose photoresist through

17、n-well mask Strip off exposed photoresist,Fabrication and Layout,Slide 32,Etch,Etch oxide with hydrofluoric acid (HF) Seeps through skin and eats bone; nasty stuff! Only attacks oxide where resist has been exposed,Fabrication and Layout,Slide 33,Strip Photoresist,Strip off remaining photoresist Use

18、mixture of acids called piranah etch Necessary so resist doesnt melt in next step,Fabrication and Layout,Slide 34,n-well,n-well is formed with diffusion or ion implantation Diffusion Place wafer in furnace with arsenic gas Heat until As atoms diffuse into exposed Si Ion Implanatation Blast wafer wit

19、h beam of As ions Ions blocked by SiO2, only enter exposed Si,Fabrication and Layout,Slide 35,Strip Oxide,Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent steps involve similar series of steps,Fabrication and Layout,Slide 36,Polysilicon,Deposit very thin layer of gate

20、 oxide 20 (6-7 atomic layers) Chemical Vapor Deposition (CVD) of silicon layer Place wafer in furnace with Silane gas (SiH4) Forms many small crystals called polysilicon Heavily doped to be good conductor,Fabrication and Layout,Slide 37,Polysilicon Patterning,Use same lithography process to pattern

21、polysilicon,Fabrication and Layout,Slide 38,Self-Aligned Process,Use oxide and masking to expose where n+ dopants should be diffused or implanted N-diffusion forms nMOS source, drain, and n-well contact,Fabrication and Layout,Slide 39,N-diffusion,Pattern oxide and form n+ regions Self-aligned proces

22、s where gate blocks diffusion Polysilicon is better than metal for self-aligned gates because it doesnt melt during later processing,Fabrication and Layout,Slide 40,N-diffusion,Historically dopants were diffused Usually ion implantation today But regions are still called diffusion,Fabrication and La

23、yout,Slide 41,N-diffusion,Strip off oxide to complete patterning step,Fabrication and Layout,Slide 42,P-Diffusion,Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact,Fabrication and Layout,Slide 43,Contacts,Now we need to wire together the devices Cover chi

24、p with thick field oxide Etch oxide where contact cuts are needed,Fabrication and Layout,Slide 44,Metallization,Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires,Fabrication and Layout,Slide 45,Layout,Chips are specified with set of masks Minimum dimensions of masks

25、determine transistor size (and hence speed, cost, and power) Feature size f = distance between source and drain Set by minimum width of polysilicon Feature size improves 30% every 3 years or so Normalize for feature size when describing design rules Express rules in terms of l = f/2 E.g. l = 0.3 mm

26、in 0.6 mm process,Fabrication and Layout,Slide 46,Simplified Design Rules,Conservative rules to get you started,Fabrication and Layout,Slide 47,Inverter Layout,Transistor dimensions specified as Width / Length Minimum size is 4l / 2l, sometimes called 1 unit For 0.6 mm process, W=1.2 mm, L=0.6 mm,Fa

27、brication and Layout,Slide 48,Summary,MOS Transistors are stack of gate, oxide, silicon Can be viewed as electrically controlled switches Build logic gates out of switches Draw masks to specify layout of transistorsNow you know everything necessary to start designing schematics and layout for a simple chip!,