ANSI ATIS 0600019-2014 Test Requirements for Pb-free Subassembly Modules.pdf

1、 AMERICAN NATIONAL STANDARD FOR TELECOMMUNICATIONS ATIS-0600019.2014 Test Requirements for Pb-free Subassembly Modules As a leading technology and solutions development organization, ATIS brings together the top global ICT companies to advance the industrys most-pressing business priorities. Through

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5、 NATIONAL STANDARD Approval of an American National Standard requires review by ANSI that the requirements for due process, consensus, and other criteria for approval have been met by the standards developer. Consensus is established when, in the judgment of the ANSI Board of Standards Review, subst

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8、National Standards Institute does not develop standards and will in no circumstances give an interpretation of any American National Standard. Moreover, no person shall have the right or authority to issue an interpretation of an American National Standard in the name of the American National Standa

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10、quire that action be taken periodically to reaffirm, revise, or withdraw this standard. Purchasers of American National Standards may receive current information on all standards by calling or writing the American National Standards Institute. Notice of Disclaimer for example, a Flip Chip BGA compon

11、ent with SnPb bumps and SnAgCu balls can be referred to as either RoHS5 or RoHS6. 3.1.2 Module: Any electronic assembly consisting of components (mechanical and/or electrical) that is preassembled with solder alloys, with the purpose of being attached or connected to another soldered assembly at a l

12、ater time. 3.1.3 Module Terminals: Module terminals refer to pins, leads, or balls on the module which interconnect the module to the next level Printed Circuit Board assembly. Figure 3. 1 - Example of Module Terminations 3.2 Acronyms, Abbreviations, leadless area array components (such as QFN, MLF,

13、 LGA, etc); BGAs with pitch less than or equal to 0.8mm; discretes greater than or equal to 2512 body size. 8. Telecommunications Infrastructure products require very long field lifetimes typically ranging from 15 to 25 years and high reliability. There are still significant unknowns relative to SAC

14、 solder joint reliability. Additionally, the greater stiffness of Pb-free solders, compared to SnPb solders, places greater stresses on the interfaces of solder joints to components and PCBs. Areas of particular concern include pad cratering, intermetallic fractures, particularly on NiAu surfaces, m

15、icrovoiding, and copper voiding that may weaken the interfaces. The following figures provide examples of some of these phenomena. NOTE: The copper voiding is not exclusive to Pb-free solders, but the added stiffness of Pb-free solders creates additional stresses on these interfaces should this void

16、ing occur. Figure 4. 1 - Example of copper voiding at Cu/Cu3Sn Interface: Left, after 20 days at 125C. Right, after 40 days 125C. (Source: Texas Instruments) ATIS-0600019.2014 5 Figure 4. 2 - Example of pad cratering Figure 4. 3 - Example of solder cracking though voids For long life products (does

17、not apply to short life products like disc drives and similar) to minimize the risk to the product lifetime, in addition to the suppliers normal qualification testing, suppliers shall age the product a minimum of 750 hours at 125C. If there are components (e.g., optical components that are inseparab

18、le from the module) that cannot tolerate 125C, then the preconditioning shall be 2000 hours at 85C. At the completion of this aging period, the module shall be subject to a mechanical shock test in accordance with JEDEC JESD22-B104 latest rev, service condition A. It is preferred that a minimum of 1

19、0 modules be subjected to this testing. A smaller sample size may be used if it is deemed adequate by the supplier, OEM, and end customer. At the end of the shock test, all modules shall be functionally tested. If failures occur, failure analysis shall be performed. The test is acceptable as long as

20、 the failures are not attributed to the defects as detailed above or specifically related to the Pb-free aspects of the design. Whether or not there are failures, a cross section of the solder joints of the largest BGA (if applicable), or otherwise largest SMT component in one of the tested modules

21、shall be completed and examined by SEM for evidence of these types of failures. If these types of failure are identified, the test is a failure, and the modules are not acceptable until appropriate corrective actions are taken and verified as successful. ATIS-0600019.2014 6 4.3 Associated Checklist

22、The following checklist is based on the above and shall be filled out as applicable for any modules being submitted for review in conjunction with this requirement. 1) For all the leaded IC and discrete components (not including BGA, QFN) used in the module, that use some form of Tin (Sn) finish (ex

23、ample finishes include Sn, SnAg, SnCu, SnBi, etc.) as the Pb-free surface finish of the component: Has the supplier performed suitable Sn whisker mitigation practices (see JEDEC JP002) and has the finish passed the Sn whisker acceptance testing requirements of JEDEC JESD-201 Class 2? _ 2) Does the m

24、odule supplier maintain a traceable and auditable record during their components supplier qualification to ensure the above Sn whisker mitigation practices and requirements are met? _ 3) If the modules external leads or pins are finished with a Tin (Sn) or Sn alloy: Has the supplier performed suitab

25、le Sn whisker mitigation practices (see JEDEC JP002) and has the finish passed the Sn whisker acceptance testing requirements of JEDEC JESD-201 Class 2? _ 4) For all Surface Mount attached modules; is the Moisture Sensitivity Level (MSL) per IPC/JEDEC J-STD-020) rating of the module based on the wor

26、st case MSL rated component used in the module? _ 5) Do all the components used internal to the module and the module itself meet the temperature and MSL requirements of the J-STD-020 and/or J-STD-075 standards? _ 6) Does the Printed Wiring Board (PWB) in the module use materials compatible with and

27、 qualified for high temperature Pb-free soldering? _ 7) Has the preconditioning called out in Section 4.2, item (8) been completed? _ 8) Have the required shock tests of all modules in accordance with JEDEC JESD22-B104 service condition A been completed after preconditioning? _ 9) After the shock te

28、st defined above, were all modules functionally tested and passed? _ 10) Has failure analysis of any failed modules been completed and the failed components and root cause (s) been identified? _ 11) Has detailed SEM examination of one of the passing modules to ensure there is no evidence of voiding

29、in the intermetallic, pad cratering, excessive solder voids, or other similar defects been completed? A summary report detailing items 8-11 of this checklist shall be provided. 12) Does the module include any of the following technologies? a) Array packages equal to or less than 0.8mm pitch? _ ATIS-

30、0600019.2014 7 b) Ceramic BGA or CuCGA component? _ c) Leadless area array component - e.g., QFN, MLF, LGA, etc.? _ d) Passives of case size 2512 or larger? _ 13) If the answer to any item in 12 is yes, has solder joint reliability evaluation per IPC-9701 on the technology component type(s) been completed? _