ANSI IEEE 1296-1994 Information Technology - Microprocessor Systems - High-Performance Synchronous 32-Bit Bus MULTIBUS II (IEEE Computer Society Document ISO IEC 10861).pdf

1、iISO/IEC 10861 : 1994ANSI/IEEE Std 1296, 1994 EditionInformation technologyMicroprocessor systemsHigh-performance synchronous32-bit bus: MULTIBUS IISponsorTechnical Committee on Microprocessors and Microcomputersof theIEEE Computer SocietyAdopted as an International Standard by theInternational Orga

2、nization for Standardizationand by theInternational Electrotechnical CommissionPublished byThe Institute of Electrical and Electronics Engineers, Inc.WITHDRAWNiiAbstract: The operation, functions, and attributes of a parallel system bus (PSB), called MULTIBUS II, aredefined. A high-performance backp

3、lane bus intended for use in multiple processor systems, the PSBincorporates synchronous, 32-bit multiplexed address/data, with error detection, and uses a 10 MHz busclock. This design is intended to provide reliable state-of-the-art operation and to allow the implementationof cost-effective, high-p

4、erformance VLSI for the bus interface. Memory, I/O, message, and geographicaddress spaces are defined. Error detection and retry are provided for messages. The message-passingdesign allows a VLSI implementation, so that virtually all modules on the bus will utilitze the bus at itshighest performance

5、32 to 40 Mbyte/s. An overview of PSB, signal descriptions, the PSB protocol,electrical characteristics, and mechanical specifications are covered.Keywords: high-performance sychronous 32-bit bus, MULTIBUS II, system bus architecturesThe Institute of Electrical and Electronics Engineers, Inc.345 East

6、 47th Street, New York, NY 10017-2394, USACopyright 1994 by the The Institute of Electrical and Electronics Engineers, Inc.All rights reserved. Published 1994. Printed in the United States of America.ISBN 1-55937-368-7No part of this publication may be reproduced in any form, in an electronic retrie

7、val system or otherwise, without theprior written permission of the publisher.WITHDRAWNiiiForewordISO (the International Organization for Standardization) and IEC (the International Electrotechnical Commission)form the specialized system for worldwide standardization. National bodies that are member

8、s of ISO or IECparticipate in the development of International Standards through technical committees established by the respectiveorganization to deal with particular fields of technical activity. ISO and IEC technical committees collaborate in fieldsof mutual interest. Other international organiza

9、tions, governmental and nongovernmental, in liaison with ISO and IEC,also take part in the work.In the field of information technology, ISO and IEC have established a joint technical committee, ISO/IEC JTC 1.Draft International Standards adopted by the joint technical committee are circulated to nat

10、ional bodies for voting.Publication as an International Standard requires approval by at least 75% of the national bodies casting a vote.In 1990, ANSI/IEEE Std 1296-1987 was adopted by ISO/IEC JTC 1, as draft International Standard ISO/IEC/DIS10861. This draft was subsequently approved by ISO/IEC JT

11、C 1 in the form of this edition, which is published asInternational Standard ISO/IEC 10861 : 1994.International Organization for Standardization/International Electrotechnical CommissionCase postale 56 CH-1211 Genve 20 SwitzerlandWITHDRAWNivIEEE Standards documents are developed within the Technical

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20、cataway, NJ 08855-1331USAIEEE standards documents may involve the use of patented technology. Their approval by the Institute ofElectrical and Electronics Engineers does not mean that using such technology for the purpose of conforming tosuch standards is authorized by the patent owner. It is the ob

21、ligation of the user of such technology to obtain allnecessary permissions.WITHDRAWNvIntroduction(This introduction is not a normative part of ISO/IEC 10861 : 1994 ANSI/IEEE Std 1296, 1994 Edition, but is included forinformation only.)In the last decade, the avalanche of new microcomputer technology

22、, especially VLSI, threatened to obsolete productsalmost before they went into production. To buffer users from this onrush of technology, Intel helped develop standardinterfaces. One of the most notable was the MULTIBUS I system bus, which was used as the basis for a standard bythe IEEE in 1983 as

23、IEEE Std 796-1983 (after going through a 5-year review and revision process).In the early 1980s, Intel recognized that the trends toward multiprocessing and more sophisticated microcomputer-based systems called for an advanced 32-bit system bus architecture. Intel called this new bus MULTIBUS II. In

24、continuing to pioneer the open systems technology, which included multiprocessing, four critical requirements wereobserved: technical credibility, processor independence, standardization, and openness to all levels of integration.Early in the development of the new bus, Intel established a “MULTIBUS

25、 II Development Consortium.” Theconsortium gave the new bus a technical credibility that few buses, especially those defined only among board vendors,can match. The companies in the consortium also represented all microprocessor families; included in the group were68020, 32032, 80386, and Z8000 boar

26、d and system users, thus ensuring that the bus is easily adaptable to virtually anymanufacturers processor.The primary benefits being sought in the creation of this new bus were high-performance multiprocessing, high systemreliability, ease-of-use by system designers, and improved cost/performance.S

27、pecific bus features were developed in response to these objectives. The 32 Mbyte/s message passing of the busprovides a bus that acts like a very high-speed network connection for multiple processors (or processor equivalents).There is a recognition that the bus is no longer to interconnect a CPU w

28、ith its memory and I/O; instead the bus is tointerconnect whole stand-alone processors with each other and with intelligent “subsystems-on-a-board.”System reliability is enhanced by the features of bus parity, synchronous operation, negative acknowledge, transferretries, geographic addressing, and a

29、dvanced backplane design. Ease-of-use by system designers is implementedprimarily through the geographic addressing, which provides for dynamic system configuration. The bus encouragesthe use of software programmable configuration options (and discourages any use of mechanical jumpers). Thestandardi

30、zation of the high-level message-passing protocol also gives the system designer an easy-to-use capability forinterprocessor communication.The cost/performance objective of the bus is delivered through its specification of a realizable 32 to 40 Mbyte/s busbandwidth. Virtually all boards designed to

31、the bus can achieve this bus utilization factor due to the high-level protocolcalled out in the specification, and thus the availability of standard, high-performance and cost-effective VLSIcomponents to actually implement this level of performance. For example, this specification and the VLSI make

32、itpossible for eight concurrent 4 megabyte/second transfers to take place on the bus. This, or other combinations oftransfers that add up to 32 Mbyte/s, demonstrate the real cost/performance advantages of the bus for multiprocessorapplications.In 1983 MULTIBUS II was introduced to the IEEE standards

33、 process as a part of the considerations for the P896(Future Bus) working group activities. In the 1984/1985 time frame the MSC (Microcomputer Standards Committee,of the TCMM) formed an independent study group for MULTIBUS II. During this time the many active participantsof the group proceeded to th

34、oroughly review and make changes to the proposed draft. In early 1986 the group wasassigned a formal project number P1296. During the remainder of 1986, the draft was passed by the Working Groupand the MSC after thorough review, discussion, and changes. In 1987, the draft was presented for Sponsor b

35、allot and,after passing, presented to the June 1987 meeting of the IEEE Standards Board.The IEEE Standards Board calls attention to the fact that there are patents claimed and/or pending on many aspects ofthis bus by Intel Corporation. IEEE takes no position with respect to patent validity. Intel Co

36、rporation has assured theIEEE that it is willing to grant a license for these patents on reasonable and nondiscriminatory terms to anyone wishingWITHDRAWNvito obtain such a license. The general terms of the license are a one-time administration fee of $100 for a nonexclusiveperpetual license. Intel

37、Corporations undertakings in this respect are on file obtained from the legal department ofIntel Corporation whose address is Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124.There were many contributors to the standards review process, but the following members deserve special m

38、ention fortheir active participation:The P1296 Working Group that prepared this standard had the following membership:Richard W. Boberg, Chair Web AugustineJack BlevinsPaul BorrillSteve CooperTom CrawfordGene FreehaufMaurice HubertHubert KirrmannKlaus MuellerJim NebusDon NickelKen SmithMichael Thomp

39、sonScott TetrickEike WaltzJanusz ZalewskiThe following members of the Technical Committee on Microprocessors and Microcomputers were on the ballotingbody:Andrew AllisonPeter J. AshendenMatt BiewerJohn BlackJack BlevinsRichard BobergPaul BorrillBradley BrownClyde CampJohn D. CharltonSteve CooperRandy

40、 DavisJ. Robert DavisShirish P. DeodharJim DunlayWayne FischerJim FlournoyGordon ForceMartin FreemanDavid GustavsonTom HarkawayDave HawleyDavid JamesLaurel KaledaRichard KarpinskiHubert KirrmanDoug KraftTom KuriharaGlen LangdonGerry LawsTom LeonardRollie LinserGary LyonsJames NebusGary NelsonDeene O

41、gdenTom PittmanShlomo Pri-TalP. ReghunathanRichard RawsonBill ShieldsMichael SmolinRobert StewartSubramanganesanMichael TeenerScott TetrickEike WaltzCarl WarrenGeorge WhiteFritz WhittingtonTom WicklundAndrew WilsonAnthony WinterTask Force Coordinators: Jack BlevinsMaurice HubertHubert KirrmannJim Ne

42、busSecretary of Working Group: Steve CooperOriginal Study Group Chairman: Paul BorrillOriginal Draft Editor: Scott TetrickWITHDRAWNviiWhen the IEEE Standards Board approved this standard on June 11, 1987, it had the following membership:Donald C. Fleckenstein, Chair Marco W. Migliaro, Vice Chair And

43、rew G. Salem, Secretary James H. BeallDennis BodsonMarshall L. CainJames M. DalyStephen R. DillonEugene P. FogartyJay ForsterKenneth D. HendrixIrvin N. HowellLeslie R. KerrJack KinnIrving KolodnyJoseph L. Koepfinger*Edward LohseJohn MayLawrence V. McCallL. Bruce McClungDonald T. Michael*L. John Rank

44、ineJohn P. RiganatiGary S. RobinsonFrank L. RoseRobert E. RountreeSava I. Sherr*William R. TackaberryWilliam B. WilkensHelen M. Wood*Member EmeritusIEEE Std 1296-1987 was approved by the American National Standards Institute on February 8, 1987 and wasreaffirmed by IEEE on March 17, 1994.WITHDRAWNvi

45、iiCLAUSE PAGE1. General overview 11.1 Scope 11.2 Normative references . 12. Definitions.23. Guide to notation.53.1 General . 53.2 Signal notation . 53.3 Figure notation . 53.4 Notation in state-flow diagrams. 63.5 Notation for multiple bit data representation . 64. PSB overview74.1 General . 74.2 Ad

46、dress/data path and system control signals 84.3 Message-passing facility 84.4 Interconnect facility . 84.5 Synchronous operation of the PSB 84.6 Bus operations on the PSB. 84.7 Central services module . 125. Signal descriptions 125.1 General . 125.2 Signal groups 126. PSB protocol .206.1 General . 2

47、06.2 Arbitration operation 216.3 Transfer operation 316.4 Exception operation . 526.5 Central control functions 566.6 State-flow diagrams . 637. Electrical characteristics .767.1 General . 767.2 AC timing specifications 777.3 DC specifications for signals . 847.4 Current limitations per connector 85

48、7.5 Pin assignments 868. Mechanical specifications .898.1 General . 898.2 Board sizes and dimensions . 908.3 Printed board layout considerations. 91WITHDRAWNixCLAUSE PAGE8.4 Front panel . 918.5 Connectors . 918.6 Backplanes . 929. IEEE 1296 System Interface specification1009.1 Overview 1009.2 Interc

49、onnect space operation 1019.3 I/O space operation 1169.4 Memory space operations 1179.5 Message space operations 11710. IEEE 1296 capabilities12810.1 Characteristic codes . 128Annex A (Informative) Recommended documentation practices.129WITHDRAWNWITHDRAWN1Information technologyMicroprocessor systemsHigh-performance synchronous 32-bit bus: MULTIBUS II1. General overview1.1 ScopeThis International Standard defines the operation, functions, and attributes of the IEEE 1296 bus standard.a) This standard defines a high-performance 32-bit synchronous bus standard.b) The bus stan