ANSI INCITS 361 ERTA-2004 Information Technology C AT Attachment with Packet Interface - 6 (ATA ATAPI-6).pdf

1、American National Standardfor Information Technology AT Attachment withPacket Interface Extensions 6(ATA/ATAPI-6)ANSI INCITS 361-2002ErratumCorrected: June 2, 2004 Secretariat: Information Technology Industry CouncilPage 1 of 9 pagesAn American National Standard implies a consensus of those substant

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6、on all standards by calling or writing the AmericanNational Standards Institute.Copyright 2004 by Information Technology Industry Council (ITI), 1250 Eye Street NW, Washington, DC 20005ANSI INCITS 361-2002ErratumPage 65, subclause 7.5.4. The direction of data flow was incorrectly described. DMA Data

7、 in is read from the data port. DMA Data out is written to the data port. Page 66 subclause 7.6.4. The direction of data flow was incorrectly described. PIO Data in is read from the data register. PIO Data out is written to the data register. Replace pages 65 - 66 with pages 65 - 66A in this erratum

8、.Page 341 subclause 9.8. Figure 33 does not show the transition HPD3:HPD4 DMARQ asserted. Clause 5.2.8 DMARQ (DMA request) describes the host behavior when DMARQ is asserted. The Figure and description omitted the state transition described in 5.2.8. In this erratum, pages 65-66A and 341-343 are rep

9、rinted with corrections.ANSI INCITS 361-2002 65 7.5 Data port 7.5.1 Address When DMACK- is asserted, CS0- and CS1- shall be negated and transfers shall be 16 bits wide. CS1 CS0 DA2 DA1 DA0 N N X X X A = asserted, N = negated, X = dont care 7.5.2 Direction This port is read/write. 7.5.3 Access restri

10、ctions This port shall be accessed for host DMA data transfers only when DMACK- and DMARQ are asserted. 7.5.4 Effect DMA data-out transfers are processed by a series of writes to this port, each write transferring the data that follows the previous write. DMA data-in transfers are processed by a ser

11、ies of reads to this port, each read transferring the data that follows the previous read. The results of a read during a DMA out or a write during a DMA in are indeterminate. 7.5.5 Functional description The data port is 16-bits in width. 7.5.6 Field/bit description 15 14 13 12 11 10 9 8 Data(15:8)

12、 7 6 5 4 3 2 1 0 Data(7:0) 7.6 Data register 7.6.1 Address CS1 CS0 DA2 DA1 DA0 N A N N N A = asserted, N = negated 7.6.2 Direction This register is read/write. ANSI INCITS 361-2002 66 7.6.3 Access restrictions This register shall be accessed for host PIO data transfer only when DRQ is set to one and

13、 DMACK- is not asserted. The contents of this register are not valid while a device is in the Sleep mode. 7.6.4 Effect PIO data-out transfers are processed by a series of writes to this register, each write transferring the data that follows the previous write. PIO data-in transfers are processed by

14、 a series of reads to this register, each read transferring the data that follows the previous read. The results of a read during a PIO out or a write during a PIO in are indeterminate 7.6.5 Functional description The data register is 16 bits wide. When a CFA device is in 8-bit PIO data transfer mod

15、e this register is 8 bits wide using only DD7 to DD0. 7.6.6 Field/bit description 15 14 13 12 11 10 9 8 Data(15:8) 7 6 5 4 3 2 1 0 Data(7:0) 7.7 Device register 7.7.1 Address CS1 CS0 DA2 DA1 DA0 N A A A N A = asserted, N = negated 7.7.2 Direction This register is read/write. 7.7.3 Access restriction

16、s This register shall be written only when both BSY and DRQ are cleared to zero and DMACK- is not asserted. The contents of this register are valid only when BSY is cleared to zero. If this register is written when BSY or DRQ is set to one, the result is indeterminate. For devices not implementing t

17、he PACKET Command feature set, the contents of this register are not valid while a device is in the Sleep mode. For devices implementing the PACKET Command feature set, the contents of this register are valid while the device is in Sleep mode. 7.7.4 Effect The DEV bit becomes effective when this reg

18、ister is written by the host or the signature is set by the device. All other bits in this register become a command parameter when the Command register is written. ANSI INCITS 361-2002 66A 7.7.5 Functional description Bit 4, DEV, in this register selects the device. Other bits in this register are

19、command dependent (see clause Error! Reference source not found.). 7.7.6 Field/bit description 7 6 5 4 3 2 1 0 Obsolete # Obsolete DEV # # # # ANSI INCITS 361-2002 341 Command packet transfer complete, nIEN=1 Command packet transfer complete, nIEN=0 HPD0: Check_Status_A PACKET command written HI4:HP

20、D0 HPD1: Send_Packet BSY = 0 & DRQ = 1 HPD0:HPD1 Data register written & command packet transfer not complete HPD1:HPD2 HPD1:HPD1 Host_Idle BSY = 0 & DRQ = 0 & REL=0 & SERV=0, no queue HPD2:HI0 Service return & service interrupt disabled HIOx:HPD2 Bus release BSY = 0 & DRQ = 0 & REL=1 & SERV=0 & nIE

21、N=0 HPD2b:HIO0 Bus release BSY = 0 & DRQ = 0 & REL=1 & SERV=0 & nIEN=1 HPD2b:HIO3 Bus release or command complete BSY = 0 & DRQ = 0 & SERV=1 HPD2:HIO5 HPD0:HPD0 BSY = 1 HPD2: Check_Status_B BSY = 0 & DRQ = 0 HPD0:HI0 Host_Idle HPD1:HPD3 nIEN=0 and INTRQ asserted HPD3:HPD2 BSY = 0 & DRQ = 1& DMARQ as

22、serted & nIEN=1 HPD3: INTRQ_wait Service return and service interrupt enabled HIOx:HPD3 BSY = 1 HPD2:HPD2 HPD4: Transfer_Data HPD2:HPD4 (All data for command transferred & nIEN=1) or (DMA burst terminated and all data for command not transferred) All data for command transferred & nIEN=0 HPD4:HPD3 H

23、PD4:HPD2 BSY = 0 & DRQ = 0 & REL=0 & SERV=0 & nIEN=1, queue HPD2a:HIO3 Command complete BSY = 0 & DRQ = 0 & REL=0 & SERV=0 & nIEN=0, queue HPD2a:HIO0 Command complete DMARQ asserted HPD3:HPD4 Figure 33 G16 Host PACKET DMA command state diagram HPD0: Check_Status_A State: This state is entered when t

24、he host has written a PACKET command to the device. ANSI INCITS 361-2002 342 When in this state, the host shall read the device Status register. When entering this state from the HI4 state, the host shall wait 400 ns before reading the Status register. Transition HPD0:HPD0: When BSY is set to one, t

25、he host shall make a transition to the HPD0: Check_Status_A state. Transition HPD0:HPD1: When BSY is cleared to zero and DRQ is set to one, then the host shall make a transition to the HPD1: Send_Packet state. Transition HPD0:HI0: When BSY is cleared to zero, DRQ is cleared to zero, REL is cleared t

26、o zero, and SERV is cleared to zero, then the command is completed and the host shall make a transition to the HI0: Host_Idle state (see Figure 19). If an error is reported, the host shall perform appropriate error recovery. HPD1: Send_Packet State: This state is entered when BSY is cleared to zero,

27、 DRQ is set to one. When in this state, the host shall write a byte of the command packet to the Data register. Transition HPD1:HPD1: When the Data register has been written and the writing of the command packet is not completed, the host shall make a transition to the HPD1: Send_Packet state. Trans

28、ition HPD1:HPD2: When the Data register has been written, the writing of the command packet is completed, and nIEN is set to one, the host shall make a transition to the HPD2: Check_Status_B state. Transition HPD1:HPD3: When the Data register has been written, the writing of the command packet is co

29、mpleted, and nIEN is cleared to zero, the host shall make a transition to the HPD3: INTRQ wait state. HPD2: Check_Status_B State: This state is entered when the host has written the command packet to the device, when INTRQ has been asserted, when a DRQ data block has been transferred, or from a serv

30、ice return when the service interrupt is disabled. When in this state, the host shall read the device Status register. When entering this state from the HPD1 or HPD4 state, the host shall wait one PIO transfer cycle time before reading the Status register. The wait may be accomplished by reading the

31、 Alternate Status register and ignoring the result. Transition HPD2:HPD2: When BSY is set to one, and DRQ is cleared to zero, the host shall make a transition to the HPD2: Check_Status_B state. Transition HPD2:HPD4: When BSY is cleared to zero, DRQ is set to one, and DMARQ is asserted and nIEN=1, th

32、en the host shall make a transition to the HPD4: Transfer_Data state. The host shall have set up the DMA engine before this transition. Transition HPD2:HI0: When BSY is cleared to zero, DRQ is cleared to zero, REL is cleared to zero, SERV is cleared to zero, and the device queue is empty, then the c

33、ommand is completed and the host shall make a transition to the HI0: Host_Idle state (see Figure 19). If an error is reported, the host shall perform appropriate error recovery. Transition HPD2a:HIO0: When BSY is cleared to zero, DRQ is cleared to zero, REL is cleared to zero, SERV is cleared to zer

34、o, nIEN is cleared to zero, and the device has a queue of released commands, then the command is completed and the host shall make a transition to the HIO0: Command completed state (see Figure 20). If an error is reported, the host shall perform appropriate error recovery. ANSI INCITS 361-2002 343 T

35、ransition HPD2a:HIO3: When BSY is cleared to zero, DRQ is cleared to zero, REL is cleared to zero, SERV is cleared to zero, nIEN is set to one, and the device has a queue of released commands, then the command is completed and the host shall make a transition to the HIO3: Command completed state (se

36、e Figure 20). If an error is reported, the host shall perform appropriate error recovery. Transition HPD2b:HIO0: When BSY is cleared to zero, DRQ is cleared to zero, REL is set to one, SERV is cleared to zero, and nIEN is cleared to zero, then the host shall make a transition to the HIO0: INTRQ_wait

37、_A state (see Figure 20). The bus has been released. Transition HPD2b:HIO3: When BSY is cleared to zero, DRQ is cleared to zero, REL is set to one, SERV is cleared to zero, and nIEN is set to one, then the host shall make a transition to the HIO3: Check_status_A state (see Figure 20). The bus has be

38、en released. Transition HPD2:HIO5: When BSY is cleared to zero, DRQ is cleared to zero, and SERV is set to one, then the host shall make a transition to the HIO5: Write_SERVICE state (see Figure 20). The command is completed or the bus has been released, and another queued command is ready for servi

39、ce. If an error is reported, the host shall perform appropriate error recovery. HPD3: INTRQ_Wait State: This state is entered when the command packet has been transmitted, when a service return is issued and the service interrupt is enabled, or when the command has completed and nIEN is cleared to z

40、ero. When in this state, the host shall wait for INTRQ to be asserted if nIEN=0 or DMARQ if nIEN=1. Transition HPD3:HPD2: When INTRQ is asserted and nIEN=0, the host shall make a transition to the HPD2: Check_Status_B state. Transition HPD3:HPD4: When DMARQ is asserted, the host shall make a transit

41、ion to the HPD4: Transfer_Data state. HPD4: Transfer_Data State: This state is entered when BSY is cleared to zero, DRQ is set to one, and DMARQ is asserted. When in this state, the host shall read or write the device Data port to transfer data. If the bus has been released, the host shall read the

42、Sector Count register to determine the Tag for the queued command to be executed. Transition HPD4:HPD2: The host shall make a transition to the HPD2: Check_Status_B state when 1) the host has transferred all data for the command and nIEN is set to one, or 2) the DMA burst has been terminated and all data for the command has not been transferred. Transition HPD4:HPD3: When all data for the request has been transferred and nIEN is cleared to zero, then the host shall make a transition to the HPD3: INTRQ_wait state.