ANSI INCITS 361-2002 Information Technology C AT Attachment with Packet Interface - 6 (ATA ATAPI-6) (ITI).pdf

1、ANSI INCITS 361-2002for Information Technology AT Attachment with Packet Interface - 6(ATA/ATAPI-6)ANSIINCITS 361-2002ANSIINCITS 361-2002American National Standardfor Information Technology AT Attachment with Packet Interface - 6(ATA/ATAPI-6)SecretariatInformation Technology Industry Council (ITI)Ap

2、proved September 20, 2002American National Standards Institute, Inc.AbstractThis standard specifies the AT Attachment Interface between host systems and storage devices. It pro-vides a common attachment interface for systems manufacturers, system integrators, software suppliers,and suppliers of inte

3、lligent storage devices. It includes the Packet Command feature set implemented bydevices commonly known as ATAPI devices.This standard maintains a high degree of compatibility with the AT Attachment Interface with Packet Inter-face - 5 (ATA/ATAPI-5), ANSI NCITS 340-2000, and while providing additio

4、nal functions, is not intendedto require changes to presently installed devices or existing software.Approval of an American National Standard requires review by ANSI that therequirements for due process, consensus, and other criteria for approval havebeen met by the standards developer.Consensus is

5、 established when, in the judgement of the ANSI Board ofStandards Review, substantial agreement has been reached by directly andmaterially affected interests. Substantial agreement means much more thana simple majority, but not necessarily unanimity. Consensus requires that allviews and objections b

6、e considered, and that a concerted effort be madetowards their resolution.The use of American National Standards is completely voluntary; theirexistence does not in any respect preclude anyone, whether he has approvedthe standards or not, from manufacturing, marketing, purchasing, or usingproducts,

7、processes, or procedures not conforming to the standards.The American National Standards Institute does not develop standards andwill in no circumstances give an interpretation of any American NationalStandard. Moreover, no person shall have the right or authority to issue aninterpretation of an Ame

8、rican National Standard in the name of the AmericanNational Standards Institute. Requests for interpretations should beaddressed to the secretariat or sponsor whose name appears on the titlepage of this standard.CAUTION NOTICE: This American National Standard may be revised orwithdrawn at any time.

9、The procedures of the American National StandardsInstitute require that action be taken periodically to reaffirm, revise, orwithdraw this standard. Purchasers of American National Standards mayreceive current information on all standards by calling or writing the AmericanNational Standards Institute

10、.American National StandardPublished byAmerican National Standards Institute, Inc.25 West 43rd Street, New York, NY 10036Copyright 2002 by Information Technology Industry Council (ITI)All rights reserved.No part of this publication may be reproduced in anyform, in an electronic retrieval system or o

11、therwise,without prior written permission of ITI, 1250 Eye Street NW, Washington, DC 20005. Printed in the United States of AmericaCAUTION: The developers of this standard have requested that holders of patents that may be re-quired for the implementation of the standard disclose such patents to the

12、 publisher. However, nei-ther the developers nor the publisher have undertaken a patent search in order to identify which, ifany, patents may apply to this standard. As of the date of publication of this standard, followingcalls for the identification of patents that may be required for the implemen

13、tation of the standard,notice of one or more such claims has been received. By publication of this standard, no positionis taken with respect to the validity of this claim or of any rights in connection therewith. The knownpatent holder(s) has (have), however, filed a statement of willingness to gra

14、nt a license underthese rights on reasonable and nondiscriminatory terms and conditions to applicants desiring to ob-tain such a license. Details may be obtained from the publisher. No further patent search is con-ducted by the developer or publisher in respect to any standard it processes. No repre

15、sentation ismade or implied that this is the only license that may be required to avoid infringement in the use ofthis standard.iContentsPageForeword . viiiIntroduction x1 Scope . 12 Normative references . 12.1 Approved references 12.2 References under development . 22.3 Other references. 23 Definit

16、ions, abbreviations, and conventions . 23.1 Definitions and abbreviations . 23.2 Conventions 54 Interface physical and electrical requirements . 104.1 Cable configuration. 104.2 Electrical characteristics . 115 Interface signal assignments and descriptions. 165.1 Signal summary 165.2 Signal descript

17、ions . 176 General operational requirements 226.1 Command delivery 226.2 Register delivered data transfer command sector addressing . 226.3 Interrupts 236.4 General feature set. 236.5 Multiword DMA . 256.6 Ultra DMA feature set . 266.7 Host determination of cable type by detecting CBLID-. 286.8 PACK

18、ET Command feature set 306.9 Overlapped feature set. 316.10 Queued feature set. 326.11 Power Management feature set . 336.12 Advanced Power Management feature set 366.13 Security Mode feature set. 366.14 Self-monitoring, analysis, and reporting technology feature set. 426.15 Host Protected Area feat

19、ure set . 446.16 CFA feature set 476.17 Removable Media Status Notification and Removable Media feature sets 486.18 Power-Up In Standby feature set . 506.19 Automatic Acoustic Management feature set. 506.20 48-bit Address feature set 516.21 Device Configuration Overlay feature set. 526.22 Media Card

20、 Pass Through Command feature set 556.23 General Purpose Logging feature set. 567 Interface register definitions and descriptions 567.1 Device addressing considerations 567.2 I/O register descriptions 63iiPage7.3 Alternate Status register. 637.4 Command register 647.5 Data port. 657.6 Data register.

21、 657.7 Device register . 667.8 Device Control register. 677.9 Error register 687.10 Features register 687.11 LBA High register . 697.12 LBA Low register 697.13 LBA Mid register. 707.14 Sector Count register . 707.15 Status register 718 Command descriptions. 748.1 CFA ERASE SECTORS. 758.2 CFA REQUEST

22、 EXTENDED ERROR CODE 778.3 CFA TRANSLATE SECTOR 798.4 CFA WRITE MULTIPLE WITHOUT ERASE 818.5 CFA WRITE SECTORS WITHOUT ERASE 828.6 CHECK MEDIA CARD TYPE. 848.7 CHECK POWER MODE 868.8 DEVICE CONFIGURATION. 888.9 DEVICE RESET . 1008.10 DOWNLOAD MICROCODE. 1018.11 EXECUTE DEVICE DIAGNOSTIC. 1038.12 FLU

23、SH CACHE 1058.13 FLUSH CACHE EXT 1068.14 GET MEDIA STATUS 1098.15 IDENTIFY DEVICE. 1108.16 IDENTIFY PACKET DEVICE . 1328.17 IDLE . 1458.18 IDLE IMMEDIATE 1478.19 MEDIA EJECT 1498.20 MEDIA LOCK . 1518.21 MEDIA UNLOCK 1538.22 NOP 1558.23 PACKET . 1568.24 READ BUFFER 1628.25 READ DMA 1638.26 READ DMA E

24、XT 1658.27 READ DMA QUEUED 1688.28 READ DMA QUEUED EXT 1728.29 READ LOG EXT. 1778.30 READ MULTIPLE. 1868.31 READ MULTIPLE EXT. 1888.32 READ NATIVE MAX ADDRESS 1918.33 READ NATIVE MAX ADDRESS EXT 1938.34 READ SECTOR(S). 1958.35 READ SECTOR(S) EXT. 1988.36 READ VERIFY SECTOR(S). 2008.37 READ VERIFY SE

25、CTOR(S) EXT. 202iiiPage8.38 SECURITY DISABLE PASSWORD . 2058.39 SECURITY ERASE PREPARE 2078.40 SECURITY ERASE UNIT . 2098.41 SECURITY FREEZE LOCK 2118.42 SECURITY SET PASSWORD 2128.43 SECURITY UNLOCK 2158.44 SEEK 2178.45 SERVICE 2188.46 SET FEATURES. 2198.47 SET MAX 2268.48 SET MAX ADDRESS EXT 2358.

26、49 SET MULTIPLE MODE 2388.50 SLEEP 2408.51 SMART . 2428.52 STANDBY. 2678.53 STANDBY IMMEDIATE 2698.54 WRITE BUFFER. 2718.55 WRITE DMA . 2728.56 WRITE DMA EXT . 2748.57 WRITE DMA QUEUED. 2778.58 WRITE DMA QUEUED EXT. 2818.59 WRITE LOG EXT 2878.60 WRITE MULTIPLE 2898.61 WRITE MULTIPLE EXT 2928.62 WRIT

27、E SECTOR(S) . 2958.63 WRITE SECTOR(S) EXT . 2979 Protocol. 3009.1 Power-on and hardware reset protocol. 3039.2 Software reset protocol. 3079.3 Bus idle protocol . 3119.4 Non-data command protocol 3229.5 PIO data-in command protocol . 3249.6 PIO data-out command protocol. 3289.7 DMA command protocol

28、. 3319.8 PACKET command protocol. 3349.9 READ/WRITE DMA QUEUED command protocol . 3469.10 EXECUTE DEVICE DIAGNOSTIC command protocol 3509.11 DEVICE RESET command protocol. 3559.12 Signature and persistence 3569.13 Ultra DMA data-in commands. 3579.14 Ultra DMA data-out commands 3599.15 Ultra DMA CRC

29、rules 3629.16 Single device configurations . 36410 Timing . 36510.1 Deskewing 36510.2 Transfer timing 365Tables1 Byte order 10ivPage2 Byte order 103 DC characteristics . 114 AC characteristics . 125 Driver types and required termination . 136 Typical series termination for Ultra DMA. 157 Interface s

30、ignal name assignments. 168 Cable type identification 199 Host detection of CBLID-. 1910 Security mode command actions . 1911 48-bit addresses. 1912 28-bit addresses. 1913 Media Card type references . 1914 Device repsonse to DOIW-/DOIR- 1915 Device is not selected, DMACK- is not asserted 1916 Device

31、 is selected, DMACK- is not asserted 1917 Device is selected, DMACK- is asserted (for Multiword DMA only) . 1918 Device 1 is selected and Device 0 is responding for Device 1. 1919 Device is in Sleep mode, DEVICE RESET is not implemented, DMACK- is not asserted. 1920 Device is in Sleep mode, DEVICE R

32、ESET is implemented, DMACK- is not asserted. 1921 Extended error codes . 1922 CFA TRANSLATE SECTOR information . 1923 Device Configuration Overlay Features register values . 1924 Device Configuration Identify data structure 1925 Device Configuration Overlay data structure 1926 Diagnostic codes 1927

33、IDENTIFY DEVICE information 1928 Minor revision number 1929 IDENTIFY PACKET DEVICE information. 1930 Automatic standby timer periods 1931 Log address defintion . 1932 General Purpose Log directory 1933 Extended Comprehensive SMART error log 1934 Extended Error Log data structure . 19v35 Command data

34、 structure 1936 Error data structure .1937 State field values.1938 Extended self-test log data structure 1939 Extended self-test log descriptor entry1940 Security password content1941 SECURITY ERASE UNIT password.1942 SECURITY SET PASSWORD data content .1943 Identifier and security level bit interac

35、tion .1944 SET FEATURES register definitions.1945 Transfer/mode values .1946 Advanced power management levels .1947 Automatic acoustic management levels1948 SET MAX Features register values.1949 SET MAX SET PASSWORD data content .1950 SMART Feature register values1951 SMART EXECUTE OFF-LINE IMMEDIAT

36、E Sector Number register values1952 Device SMART data structure 1953 Off-line data collection status byte values.1954 Self-test execution status byte values.1955 Log address definition.1956 SMART log directory.1957 SMART summary error log sector 1958 Error log data structure .1959 Command data struc

37、ture 1960 Error data structure .1961 State field values.1962 Comprehensive error log 1963 Self-test log data structure 1964 Self-test log descriptor entry .1965 Equations for parallel generation of a CRC polynomial 1966 Register transfer to/from device1967 PIO data transfer to/from device .1968 Mult

38、iword DMA data transfer 1969 Ultra DMA data burst timing requirements1970 Ultra DMA data burst timing descriptions19vi71 Ultra DMA sender and recipient IC timing requirements.19Figures1 State diagram convention .82 Ultra DMA termination with pull-up or pull-down.153 Cable select example194 Alternate

39、 cable select example .195 Example configuration of a system with a 40-conductor cable .196 Example configuration of a system where the host detects a 40-conductor cable .197 Example configuration of a system where the host detects an80-conductor cable .198 Power management state diagram 199 Securit

40、y mode state diagram .1910 SET MAX security state diagram 1911 Device Configuration Overlay state diagram 1912 Overall host protocol state sequence1913 Overall device protocol state sequence 1914 Host power-on or hardware reset state diagram.1915 Device power-on or hardware reset state diagram .1916

41、 Host software reset state diagram 1917 Device 0 software reset state diagram1918 Device 1 software reset state diagram1919 Host bus idle state diagram 1920 Additional host bus idle state diagram with overlap or overlap and queuing1921 Device bus idle state diagram.1922 Additional device bus idle st

42、ate diagram with overlap or overlap and queuing1923 Host non-data state diagram.1924 Device non-data state diagram .1925 Host PIO data-in state diagram.1926 Device PIO data-in state diagram .1927 Host PIO data-out state diagram 1928 Device PIO data-out state diagram.1929 Host DMA state diagram.1930

43、Device DMA state diagram .1931 Host PACKET non-data and PIO data command state diagram 1932 Device PACKET non-data and PIO data command state diagram.1933 Host PACKET DMA command state diagram.19vii34 Device PACKET DMA command state diagram .1935 Host DMA QUEUED state diagram 1936 Device DMA QUEUED

44、command state diagram 1937 Host EXECUTE DEVICE DIAGNOSTIC state diagram 1938 Device 0 EXECUTE DEVICE DIAGNOSTIC state diagram .1939 Device 1 EXECUTE DEVICE DIAGNOSTIC command state diagram.1940 Host DEVICE RESET command state diagram1941 Device DEVICE RESET command state diagram 1942 Example paralle

45、l CRC generator 1943 Register transfer to/from device1944 PIO data transfer to/from device .1945 Initiating a Multiword DMA data burst .1946 Sustaining a Multiword DMA data burst1947 Device terminating a Multiword DMA data burst.1948 Host terminating a Multiword DMA data burst 1949 Initiating an Ult

46、ra DMA data-in burst .1950 Sustained Ultra DMA data-in burst .1951 Host pausing an Ultra DMA data-in burst .1952 Device terminating an Ultra DMA data-in burst.1953 Host terminating an Ultra DMA data-in burst 1954 Initiating an Ultra DMA data-out burst.1955 Sustained Ultra DMA data-out burst .1956 De

47、vice pausing an Ultra DMA data-out burst1957 Host terminating an Ultra DMA data-out burst 1958 Device terminating an Ultra DMA data-out burst 19AnnexesA Connectors and cable assemblies 19B Device determination of cable type.19C Signal integrity and UDMA implementation guide.19D Bibliography 19E ATA

48、command set summary.19viiiForeword (This foreword is not part of ANSI INCITS 361-2002.)This AT Attachment with Packet Interface - 6 (ATA/ATAPI-6) standard is designed tomaintain a high degree of compatibility with the AT Attachment with Packet Interface- 5 (ATA/ATAPI-5) standard.This standard was de

49、veloped by the ATA ad hoc working group of INCITS during2000 and 2001. The standards approval process started in 2001. This document in-cludes annexes that are informative and are not considered part of the standard.Requests for interpretation, suggestions for improvement and addenda, or defect re-ports are welcome. They should be sent to the INCITS Secretariat, Information Tech-nology Industry Council, 1250 Eye Street, NW, Suite 200, Washington, DC 20005-3922.This standard was processed and approved for submittal to ANSI by InterNationalCommittee for Information Technology Standards (IN