ANSI INCITS 397 V2-2005 for Information Technology AT Attachment with Packet Interface - 7 Volume 2 - Parallel Transport Protocols and Physical Interconnect (ATA ATAPI-7 V2).pdf

1、American National StandardDeveloped byfor Information Technology AT Attachment with Packet Interface - 7Volume 2 - Parallel Transport Protocolsand Physical Interconnect(ATA/ATAPI-7 V2) ANSI INCITS 397-2005 (Vol. 2)ANSIINCITS397-2005(Vol. 2)ANSIINCITS 397-2005(Vol. 2)American National Standardfor Inf

2、ormation Technology AT Attachment with Packet Interface - 7Volume 2 - Parallel Transport Protocolsand Physical Interconnect(ATA/ATAPI-7 V2)SecretariatInformation Technology Industry CouncilApproved February 7, 2005American National Standards Institute, Inc.AbstractThis standard specifies the AT Atta

3、chment Interface between host systems and storage devices. It pro-vides a common attachment interface for systems manufacturers, system integrators, software suppliers,and suppliers of intelligent storage devices. It includes the Packet Command feature set implemented bydevices commonly known as ATA

4、PI devices. It also includes the Serial Transport Protocols and PhysicalInterconnect for AT Atachment devices commonly known as Serial ATA.This standard maintains a high degree of compatibility with the AT Attachment Interface with Packet Inter-face - 6 (ATA/ATAPI-6), ANSI INCITS 361-2002, and while

5、 providing additional functions, is not intendedto require changes to presently installed devices or existing software.Approval of an American National Standard requires review by ANSI that therequirements for due process, consensus, and other criteria for approval havebeen met by the standards deve

6、loper.Consensus is established when, in the judgement of the ANSI Board ofStandards Review, substantial agreement has been reached by directly andmaterially affected interests. Substantial agreement means much more thana simple majority, but not necessarily unanimity. Consensus requires that allview

7、s and objections be considered, and that a concerted effort be madetowards their resolution.The use of American National Standards is completely voluntary; theirexistence does not in any respect preclude anyone, whether he has approvedthe standards or not, from manufacturing, marketing, purchasing,

8、or usingproducts, processes, or procedures not conforming to the standards.The American National Standards Institute does not develop standards andwill in no circumstances give an interpretation of any American NationalStandard. Moreover, no person shall have the right or authority to issue aninterp

9、retation of an American National Standard in the name of the AmericanNational Standards Institute. Requests for interpretations should beaddressed to the secretariat or sponsor whose name appears on the titlepage of this standard.CAUTION NOTICE: This American National Standard may be revised orwithd

10、rawn at any time. The procedures of the American National StandardsInstitute require that action be taken periodically to reaffirm, revise, orwithdraw this standard. Purchasers of American National Standards mayreceive current information on all standards by calling or writing the AmericanNational S

11、tandards Institute.American National StandardPublished byAmerican National Standards Institute, Inc.25 West 43rd Street, New York, NY 10036Copyright 2005 by Information Technology Industry Council (ITI)All rights reserved.No part of this publication may be reproduced in anyform, in an electronic ret

12、rieval system or otherwise,without prior written permission of ITI, 1250 Eye Street NW, Washington, DC 20005. Printed in the United States of AmericaCAUTION: The developers of this standard have requested that holders of patents that may berequired for the implementation of the standard disclose suc

13、h patents to the publisher. However,neither the developers nor the publisher have undertaken a patent search in order to identifywhich, if any, patents may apply to this standard. As of the date of publication of this standardand following calls for the identification of patents that may be required

14、 for the implementation ofthe standard, no such claims have been made. No further patent search is conducted by the de-veloper or publisher in respect to any standard it processes. No representation is made or impliedthat licenses are not required to avoid infringement in the use of this standard.iC

15、ontentsPageForeword . xiiiIntroduction .xvi1 Scope. 12 Normative references. 32.1 Approved references 32.1.1 ANSI References . 32.1.2 ISO References . 32.2 References under development. 32.3 Other references 33 Definitions, abbreviations, and conventions. 53.1 Definitions and abbreviations. 53.2 Con

16、ventions. 83.2.1 Precedence 93.2.2 Lists 93.2.3 Keywords . 93.2.4 Numbering . 103.2.5 Signal conventions. 103.2.6 Bit conventions. 103.2.7 State diagram conventions 113.2.8 Timing conventions 123.2.9 Byte ordering for data transfers . 123.2.10 Byte, word and DWORD Relationships 144 General command o

17、perational requirements (See Volume 1). 155 Interface register descriptions (See Volume 1) 156 Command descriptions (See Volume 1) 157 Parallel interface physical and electrical requirements 167.1 Cable configuration 167.2 Electrical characteristics 167.2.1 AC characteristics measurement techniques.

18、 187.2.1.1 Slew rate 187.2.1.2 VSSO197.2.2 Driver types and required termination 207.2.3 Electrical characteristics for Ultra DMA 207.2.3.1 Cable configuration 217.2.3.2 Series termination required for Ultra DMA. 217.2.3.3 PCB trace requirements for Ultra DMA 227.3 Connectors and cable asemblies. 23

19、7.3.1 40-pin Connector . 237.3.1.1 40-conductor cable 267.3.1.2 80-conductor cable assembly using the 40-pin connector. 277.3.2 4-pin power connector . 337.3.2.1 Mating performance. 35iiPage7.3.3 Unitized connectors . 357.3.4 50-pin 2.5 inch form factor style connector 377.3.5 68-pin PCMCIA connecto

20、r . 387.3.5.1 Signals . 397.3.5.2 Signal descriptions. 397.3.5.3 Removability considerations 417.3.6 CompactFlashTMconnector. 427.3.7 1.8 inch 3.3V parallel connector 427.4 Physical form factors . 457.4.1 3.5“ form factor 457.4.1.1 Connector location for 3.5“ form factor 467.4.2 2.5“ form factor 467

21、.4.2.1 Connector location for 2.5“ form factor 497.4.3 1.8“ PCMCIA form factor . 507.4.3.1 Connector location for 1.8“ PCMCIA form factor . 507.4.4 1.8“ 5V parallel form factor 507.4.4.1 Connector location for 1.8“ 5V parallel form factor 527.4.5 1.8“ 3.3V parallel form factor . 537.4.5.1 Connector

22、location for 1.8“ 3.3V parallel form factor . 557.4.6 5.25“ form factor 557.4.6.1 5.25“ HDD form factor 557.4.6.2 5.25 inch CD-ROM form factor 578 Parallel interface signal assignments and descriptions . 598.1 Signal summary . 598.2 Signal descriptions. 608.2.1 CS(1:0)- (Chip select) . 608.2.2 DA(2:

23、0) (Device address) . 608.2.3 DASP- (Device active, device 1 present). 608.2.4 DD(15:0) (Device data). 608.2.5 DIOR-:HDMARDY-:HSTROBE (Device I/O read:Ultra DMA ready:Ultra DMA data strobe) . 608.2.6 DIOW-:STOP (Device I/O write:Stop Ultra DMA burst) . 608.2.7 DMACK- (DMA acknowledge) . 608.2.8 DMAR

24、Q (DMA request) . 608.2.9 INTRQ (Device interrupt) . 618.2.10 IORDY:DDMARDY-:DSTROBE (I/O channel ready:Ultra DMA ready:Ultra DMA data strobe) . 618.2.11 PDIAG-:CBLID- (Passed diagnostics:Cable assembly type identifier). 618.2.12 RESET- (Hardware reset) 638.2.13 CSEL (Cable select) 638.2.13.1 CSEL w

25、ith 40-conductor cable 648.2.13.2 CSEL with 80-conductor cable 649 Parallel interface general operational requirements 659.1 Interrupts 659.2 Multiword DMA 669.3 Ultra DMA feature set 669.3.1 Overview 66iiiPage9.3.2 Phases of operation . 679.3.2.1 Ultra DMA burst initiation phase rules 689.3.2.2 Dat

26、a transfer phase rules. 689.3.2.3 Ultra DMA burst termination phase rules . 689.4 Host determination of cable type by detecting CBLID- 6810 Parallel interface register addressing. 7111 Parallel interface transport protocol . 7811.1 Power-on and hardware reset protocol 8111.2 Software reset protocol

27、8511.3 Bus idle protocol. 8911.4 Non-data command protocol 10011.5 PIO data-in command protocol 10211.6 PIO data-out command protocol 10611.7 DMA command protocol. 11011.8 PACKET command protocol 11311.9 READ/WRITE DMA QUEUED command protocol. 12511.10 EXECUTE DEVICE DIAGNOSTIC command protocol 1291

28、1.11 DEVICE RESET command protocol 13411.12 Ultra DMA data-in commands 13511.12.1 Initiating an Ultra DMA data-in burst 13511.12.2 The data-in transfer 13611.12.3 Pausing an Ultra DMA data-in burst. 13611.12.3.1 Device pausing an Ultra DMA data-in burst. 13611.12.3.2 Host pausing an Ultra DMA data-i

29、n burst. 13611.12.4 Terminating an Ultra DMA data-in burst. 13711.12.4.1 Device terminating an Ultra DMA data-in burst 13711.12.4.2 Host terminating an Ultra DMA data-in burst . 13711.13 Ultra DMA data-out commands 13811.13.1 Initiating an Ultra DMA data-out burst 13811.13.2 The data-out transfer 13

30、911.13.3 Pausing an Ultra DMA data-out burst 13911.13.3.1 Host pausing an Ultra DMA data-out burst 13911.13.3.2 Device pausing an Ultra DMA data-out burst. 13911.13.4 Terminating an Ultra DMA data-out burst 13911.13.4.1 Host terminating an Ultra DMA data-out burst . 13911.13.4.2 Device terminating a

31、n Ultra DMA data-out burst 14011.14 Ultra DMA CRC rules. 14012 Parallel interface timing 14312.1 Deskewing 14312.2 Transfer timing . 14312.2.1 Register transfers. 14312.2.2 PIO data transfers 145ivPage12.2.3 Multiword DMA data transfer . 14812.2.3.1 Initiating a Multiword DMA data burst 14812.2.3.2

32、Sustaining a Multiword DMA data burst. 15012.2.3.3 Device terminating a Multiword DMA data burst 15112.2.3.4 Host terminating a Multiword DMA data burst . 15212.2.4 Ultra DMA data transfer . 15312.2.4.1 Initiating an Ultra DMA data-in burst 15612.2.4.2 Sustained Ultra DMA data-in burst 15712.2.4.3 H

33、ost pausing an Ultra DMA data-in burst 15812.2.4.4 Device terminating an Ultra DMA data-in burst . 15912.2.4.5 Host terminating an Ultra DMA data-in burst . 16012.2.4.6 Initiating an Ultra DMA data-out burst 16112.2.4.7 Sustained Ultra DMA data-out burst 16212.2.4.8 Device pausing an Ultra DMA data-

34、out burst 16312.2.4.9 Host terminating an Ultra DMA data-out burst. 16412.2.4.10 Device terminating an Ultra DMA data-out burst . 16513 Serial interface overview (See Volume 3) 16614 Serial interface physical layer (See Volume 3) 16615 Serial interface link layer (See Volume 3) 16616 Serial interfac

35、e transport layer (See Volume 3). 16617 Serial interface device command layer (See Volume 3) 16618 Host command layer (See Volume 3) 16619 Serial interface host adapter register interface (See Volume 3) 16620 Serial interface error handling (See Volume 3) 166AnnexesA Bibliography (See Volume 1) . 16

36、7B Command Set Summary (See Volume 1) . 167C Design and Programming Consiferations for Large Physical Sector Sizes (See Volume 1) 167D Device Determionation of Cable Type 167D.1 Overview 167D.2 Sequence for device detection of installed capacitor. 168D.3 Using the combination of methods for detectin

37、g cable type 169E Signal Integrity and UDMA Guide 171E.1 Introduction 171E.2 The issues . 171E.2.1 Timing 171E.2.1.1 Cabling. 172E.2.1.2 Skew 172E.2.1.3 Source-terminated bus 173E.2.1.4 Timing measurements for the 80-conductor cable assembly 178E.2.1.5 Simulations for the 80-conductor cable assembly

38、 . 178vPageE.2.2 Crosstalk 179E.2.2.1 Capacitive coupling 180E.2.2.2 Inductive coupling 182E.2.2.3 Mixed capacitive and inductive coupling 183E.2.2.4 Crosstalk from distributed coupling 183E.2.2.5 Measuring crosstalk in a system 189E.2.2.6 System design considerations to minimize crosstalk . 189E.2.

39、3 Ground/Power Bounce. 190E.2.4 Ringing and data settling time (DST) for the 40-conductor cable assembly 192E.2.4.1 Controlling ringing on a 40-conductor cable assembly 195E.2.4.2 STROBE lines on the 40-conductor cable . 197E.3 System Guidelines for Ultra DMA 198E.3.1 System capacitance . 198E.3.2 P

40、ull-up and pull-down resistors 198E.3.3 Cables and connectors 198E.3.4 Host PCB and IC design 199E.3.5 Sender and recipient component I/Os 199E.4 Ultra DMA electrical characteristics . 200E.4.1 DC characteristics 200E.4.1.1 ViHmaximum . 200E.4.1.2 VDD3(modes higher than 4 only) . 201E.4.1.3 VoH2 min

41、imum and maximum (modes higher than 4 only) 201E.4.1.4 V+ and V- thresholds (modes higher than 4 only). 201E.4.1.5 Hysteresis (VHYS) (modes higher than 4 only) 202E.4.2 AC characteristics 202E.4.2.1 SRISE2and SFALL2(modes higher than 4 only) 202E.4.2.2 VDSSOand VHSSO(modes higher than 4 only) 202E.4

42、.2.3 Cratio(modes higher than 4 only) . 202E.5 Ultra DMA timing and protocol . 203E.5.1 Ultra DMA timing assumptions. 203E.5.1.1 System delays and skews 203E.5.1.2 IC and PCB timings, delays, and skews 204E.5.2 Ultra DMA timing parameters. 206E.5.2.1 Typical average two-cycle time (t2CYCTYP) 206E.5.

43、2.2 Cycle time (tCYC) 206E.5.2.3 -Cycle time (t2CYC) . 207E.5.2.4 Data setup time (tDS) 207E.5.2.5 Data hold time (tDH) . 208E.5.2.6 Data valid setup time (tDVS) . 208E.5.2.7 Data hold time (tDVH) 209E.5.2.8 CRC word setup time (tCS) (modes higher than 4 only). 209E.5.2.9 CRC word hold time (tCH) (m

44、odes higher than 4 only). 210E.5.2.10 CRC word valid setup time (tCVS) (modes higher than 4 only). 210E.5.2.11 CRC word valid hold time (tCVH) (modes higher than 4 only) 210viPageE.5.2.12 First DSTROBE time (tZFS) (modes higher than 4 only) 210E.5.2.13 Data enabled to the first DSTROBE edge time (tD

45、ZFS) (modes higher than 4 only) . 211E.5.2.14 First DSTROBE time (tFS) 211E.5.2.15 Limited interlock time (tLI) 212E.5.2.16 Limited interlock time with minimum (tMLI). 212E.5.2.17 Unlimited interlock time (tUI) 212E.5.2.18 Maximum driver release time (tAZ). 212E.5.2.19 Minimum delay time (tZAH). 213

46、E.5.2.20 Minimum driver assert/negate time (tZAD) 214E.5.2.21 Envelope time (tENV) 214E.5.2.22 STROBE to DMARDY- time (tSR) 215E.5.2.23 DMARDY- to final STROBE time (tRFS). 215E.5.2.24 DMARDY- to pause time (tRP) . 216E.5.2.25 Maximum IORDY release time (tIORDYZ) . 217E.5.2.26 Minimum IORDY assert t

47、ime (tZIORDY) 217E.5.2.27 Setup and hold before DMACK- time (tACK) 218E.5.2.28 STROBE to DMARQ/STOP time (tSS). 218E.5.2.29 Data setup time at IC component (tDSIC) (modes higher than 4 only) . 218E.5.2.30 Data hold time at IC component (tDHIC) (modes higher than 4 only) . 219E.5.2.31 Data valid setu

48、p time at IC component (tDVSIC) (modes higher than 4 only) . 219E.5.2.32 Data valid hold time at component IC (tDVHIC) (modes higher than 4 only) . 219E.5.3 Ultra DMA Protocol Considerations . 219E.5.3.1 Recipient pauses . 219E.5.3.2 CRC calculation and comparison 221E.5.3.3 The IDENTIFY DEVICE and

49、IDENTIFY PACKET DEVICE commands . 222E.5.3.4 STROBE minimums and maximums . 222E.5.3.5 Typical STROBE cycle timing 223E.5.3.6 Holding data to meet setup and hold times . 223E.5.3.7 Opportunities for the host to delay the start of a burst. 224E.5.3.8 Maximums on all control signals from the device 224E.6 Cable detection 224E.6.1 80-conductor cable assembly electrical feature. 224E.6.2 Host determination of cable assembly type . 224E.6.3 Device determination of cable assembly type . 225E.6.3.1 Capacitor on CBLID- 225F Register Selection Address Summary (See Volume 3) . 228G Sample Code for