ANSI INCITS370-2004 Information technology - ATA ATAPI Host Adapters Standard (ATA - Adapter)《信息技术.ATA ATAPI主机适配器标准》.pdf

1、American National StandardDeveloped byfor Information Technology ATA/ATAPI Host Adapters Standard (ATA - Adapter)ANSI INCITS 370-2004ANSIINCITS370-2004Copyright American National Standards Institute Provided by IHS under license with ANSINot for ResaleNo reproduction or networking permitted without

2、license from IHS-,-,-Copyright American National Standards Institute Provided by IHS under license with ANSINot for ResaleNo reproduction or networking permitted without license from IHS-,-,-ANSIINCITS 370-2004American National Standardfor Information Technology -ATA/ATAPI Host Adapters Standard(ATA

3、 - Adapter)SecretariatInformation Technology Industry CouncilApproved February 19, 2004American National Standards Institute, Inc.AbstractThis standard specifies the Host System Interface used to control AT Attachment Interface devices. It pro-vides a common Programming interface for systems manufac

4、turers, system integrators, software suppli-ers, and suppliers of intelligent storage devices. Copyright American National Standards Institute Provided by IHS under license with ANSINot for ResaleNo reproduction or networking permitted without license from IHS-,-,-Approval of an American National St

5、andard requires review by ANSI that therequirements for due process, consensus, and other criteria for approval havebeen met by the standards developer.Consensus is established when, in the judgement of the ANSI Board ofStandards Review, substantial agreement has been reached by directly andmaterial

6、ly affected interests. Substantial agreement means much more thana simple majority, but not necessarily unanimity. Consensus requires that allviews and objections be considered, and that a concerted effort be madetowards their resolution.The use of American National Standards is completely voluntary

7、; theirexistence does not in any respect preclude anyone, whether he has approvedthe standards or not, from manufacturing, marketing, purchasing, or usingproducts, processes, or procedures not conforming to the standards.The American National Standards Institute does not develop standards andwill in

8、 no circumstances give an interpretation of any American NationalStandard. Moreover, no person shall have the right or authority to issue aninterpretation of an American National Standard in the name of the AmericanNational Standards Institute. Requests for interpretations should beaddressed to the

9、secretariat or sponsor whose name appears on the titlepage of this standard.CAUTION NOTICE: This American National Standard may be revised orwithdrawn at any time. The procedures of the American National StandardsInstitute require that action be taken periodically to reaffirm, revise, orwithdraw thi

10、s standard. Purchasers of American National Standards mayreceive current information on all standards by calling or writing the AmericanNational Standards Institute.American National StandardPublished byAmerican National Standards Institute, Inc.25 West 43rd Street, New York, NY 10036Copyright 2004

11、by Information Technology Industry Council (ITI)All rights reserved.No part of this publication may be reproduced in anyform, in an electronic retrieval system or otherwise,without prior written permission of ITI, 1250 Eye Street NW, Washington, DC 20005. Printed in the United States of AmericaCAUTI

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15、. Details may be obtained from the publisher. No further patent search is con-ducted by the developer or publisher in respect to any standard it processes. No representation ismade or implied that this is the only license that may be required to avoid infringement in the use ofthis standard.Copyrigh

16、t American National Standards Institute Provided by IHS under license with ANSINot for ResaleNo reproduction or networking permitted without license from IHS-,-,-iContentsPageForeword .ivIntroduction vii1 Scope . 12 Normative References . 12.1 Content Imported from Normative Standards . 12.2 Industr

17、y Standard References 13 Definitions, Abbreviations, and Conventions 23.1 Definitions and Abbreviations 23.2 Conventions 54 ATA Host Adapters 74.1 Adapter Types. 74.2 Adapter Modes 75 ISA Bus Adapter. 85.1 Mode of Operation 85.2 Detection . 85.3 Adapter Set Up 85.4 ATA Bus Timings 85.5 Electrical an

18、d Physical 85.6 Registers . 86 PCI Compatibility and PCI-Native Mode Bus Master Adapters 86.1 Mode of Operation 86.2 Detection . 86.3 Adapter Set Up 86.4 ATA Bus Timings 96.5 Electrical and Physical 96.6 PCI Registers 96.7 ATA Bus Master Registers 126.8 Interrupt Line Considerations 156.9 Bus Master

19、 Operation . 157 Automatic Direct Memory Access (ADMA) Adaptors - General Description 177.1 Background . 177.2 The ADMA Engine 177.3 ADMA Overview 187.4 ADMA PCI Registers. 22Copyright American National Standards Institute Provided by IHS under license with ANSINot for ResaleNo reproduction or netwo

20、rking permitted without license from IHS-,-,-iiPage7.5 ADMA Registers 317.6 Auto DMA Mode Data Structures 377.7 ADMA Operation. 447.8 Host Operation 487.9 Resets. 50AnnexesA Programming Guidelines 51B PCI Compatibility and PCI-Native Mode Bus Master Adapter Configuration 55Tables1 Compatibility Mode

21、 Standard I/O Register Addresses. 72 PCI Compatibility and PCI-Native Mode Bus Master Adapters Configuration Registers 93 PCI Compatibility and PCI-Native Mode Bus Master Adapters Class Code Registers. 94 PCI Adapter bit definitions in Programming Interface Byte 105 ATA Bus Master Register Offsets 1

22、26 ATA Bus Master Command Register. 137 Bus Master ATA Status Register . 148 PRD Table Pointer Register. 159 Physical Region Descriptor Table Entry. 1510 Adapter Bus Master Status Register bits . 1611 ADMA PCI Configuration Space Header Registers . 2312 ADMA PCI Command Register 2413 ADMA PCI Status

23、 Register 2414 ADMA PCI Class Code 2515 ADMA Power Management Registers . 2816 ADMA Power Management Capability Register 2917 ADMA Power Management Control/Status Register . 2918 ADMA Power Management State Control bits. 2919 ADMA Memory Mapped Registers. 3220 ADMA Control Register 3421 ADMA Status

24、Register . 3522 CPB Structure 3823 ATA Register Field. 4024 APRD Data Structure. 42Copyright American National Standards Institute Provided by IHS under license with ANSINot for ResaleNo reproduction or networking permitted without license from IHS-,-,-iiiPage25 PCI Configuration Registers. 5526 ATA

25、 Timing Register 5627 Device 1 ATA Timing Register . 5728 UDMA Control Register 5829 UDMA Timing Register. 5930 UDMA Control Register 60Figures1 State Diagram Convention . 62 ADMA Data Structures . 203 Power Management State Transitions . 304 CPB States. 435 ADMA State Transitions . 456 Host Softwar

26、e States 48Copyright American National Standards Institute Provided by IHS under license with ANSINot for ResaleNo reproduction or networking permitted without license from IHS-,-,-ivForeword (This foreword is not part of American National Standard ANSI INCITS 370-2004.)This standard was developed b

27、y Technical Committee T13 on ATA Storage Inter-faces of the InterNational Committee for Information Technology Standards(INCITS), starting in 2001. This document includes two annexes that are informativeand are not considered part of the standard.Requests for interpretation, suggestions for improvem

28、ent and addenda, or defect re-ports are welcome. They should be sent to the INCITS Secretariat, Information Tech-nology Industry Council, 1250 Eye Street, NW, Suite 200, Washington, DC 20005-3922.This standard was processed and approved for submittal to ANSI by the InterNation-al Committee for Infor

29、mation Technology Standards, INCITS. Committee approval ofthe standard does not necessarily imply that all committee members voted for ap-proval. At the time it approved this standard, the INCITS Committee had the followingmembers:Karen Higginbottom, ChairJennifer Garner, SecretaryOrganization Repre

30、sented Name of RepresentativeApple Computer, Inc. David MichaelFarance, Inc . Frank FaranceHewlett-Packard Company. Karen HigginbottomScott Jameson (Alt.)Steve Mills (Alt.)EIA Edward Mikoski, Jr.Suan Hoyler (Alt.)IBM Corporation . Ronald F. SillettiInstitute for Certification of Computer Professiona

31、ls Kenneth M. ZemrowskiThomas Kurihara (Alt.)IEEE . Judith GormanRichard Holleman (Alt.)Robert Pritchard (Alt.)Intel Corporation. Philip WennblomDave Thewlis (Alt.)Microsoft Corporation . Mike KsarFrank Camara (Alt.)National Institute of Standards the device used bits 0-6. This register is no longer

32、 used in the ATA standard. 4.2.1.2 PCI-Native Mode This mode is only applicable to adapters bridging to the PCI bus. In this mode the control of the transfer is through the ATA Command and Control Block Registers and registers in the adapter. The addresses of the Command or Control block are defined

33、 in the Base Address Register (BAR) of the adapter and are defined by Copyright American National Standards Institute Provided by IHS under license with ANSINot for ResaleNo reproduction or networking permitted without license from IHS-,-,-ANSI INCITS 370-2004 8 the Host software. There is only one

34、Host interrupt line for all the channels attached to an adapter. There is no restriction on the number of adapters there can be in the system. 4.2.2 ADMA Mode In this mode the ATA Command and Control Block registers are not accessible to the Host. Control is exercised through a data structure held i

35、n host memory and adapter registers. 5 ISA Bus Adapter This type of adapter is commonly called a paddle card for use in PC compatible systems. The function of the adapter is to decode the I/O addresses appropriate to the channels it controls. 5.1 Mode of Operation Only operates in Compatibility Mode

36、. 5.2 Detection There is no standard method to detect the presence of this type of adapter. Software may be able to detect the presence of ATA drives by examining the ATA registers at the standard I/O addresses and thereby infer the presence of an adapter. 5.3 Adapter Set Up There is no standard met

37、hod used to set up these adapters. In most cases the I/O address banks are set by hard jumpers or by vendor specific registers. 5.4 ATA Bus Timings ISA timings. No programmable timing is available. 5.5 Electrical and Physical The electrical and physical specifications of the ATA bus are defined in t

38、he ATA Standard; the ISA bus characteristics are defined in the ISA Spec. 5.6 Registers The compatibility register set shall be implemented. 6 PCI Compatibility and PCI-Native Mode Bus Master Adapters PCI Adapters conforming to this standard may operate in Compatibility or Native-PCI Mode. Some adap

39、ters can be configured to operate in either mode; some are fixed to one of the modes. The mode configuration may be determined from the PCI Configuration registers. 6.1 Mode of Operation 6.1.1 Compatibility Mode Adapters operating in Compatibility Mode support two channels conforming to the Primary

40、and Secondary channel address and have a separate IRQ for each channel. 6.1.2 PCI-Native Mode Adapters operating in Compatibility Mode may support one or two channels. 6.2 Detection The Class Code fields determine the capabilities. 6.3 Adapter Set Up The Class Code fields determine the capabilities

41、of an adapter and may be used to configure the channels to Compatibility or PCI-Native mode. The PCI BARs may be used to configure and determine the I/O addresses to use to access the ATA and adapter registers. Copyright American National Standards Institute Provided by IHS under license with ANSINo

42、t for ResaleNo reproduction or networking permitted without license from IHS-,-,-ANSI INCITS 370-2004 9 6.4 ATA Bus Timings Determination of the ATA PIO timings, DMA protocols and DMA timings supported is vendor specific. Consequently configuring these attributes is vendor specific. 6.5 Electrical a

43、nd Physical The electrical and physical specifications of the ATA bus are defined in the ATA Standard; the PCI bus characteristics are defined in the PCI SPEC specification. 6.6 PCI Registers The PCI Adapter implements a subset of the PCI standard type 00h configuration header register set. All regi

44、sters have the standard meaning as defined in the PCI Specification, Issue 2.2. The registers with specific meanings with respect to this standard are defined below. Register contents that are otherwise defined in the PCI standard are indicates as “PCI”. Fields marked reserved are all zeros and read

45、 only. Table 2 PCI Compatibility and PCI-Native Mode Bus Master Adapters Configuration Registers Byte Offset Bits 31-24 Bits 23-16 Bits 15-8 Bits 7-0 00h PCI 04h PCI 08h Class Code PCI 0Ch PCI 10h Base Address 0 - Base Address of Cmd-Block Regs, ATA Channel X 14h Base Address 1 - Base Address of Con

46、trol Regs, ATA Channel X 18h Base Address 2 - Base Address of Cmd-Block Regs, ATA Channel Y 1Ch Base Address 3 - Base Address of Control Regs, ATA Channel Y 20h Base Address 4 - Base Address of ATA Bus Master Registers 24h Base Address 5 Vendor Specific 28h PCI 2Ch Subsystem ID PCI 30h PCI 34h PCI 3

47、8h PCI 3Ch PCI Interrupt Line 6.6.1 PCI Class Code Address Offset 09h Size 24 bits Table 3 PCI Compatibility and PCI-Native Mode Bus Master Adapters Class Code Registers Byte Offset Description Attribute Value 09h Programming Interface Code See Table 4 See Table 4 0Ah Sub-class Code Read Only 01h ID

48、E 0Bh Base-Class Code Read Only 01h Mass Storage Copyright American National Standards Institute Provided by IHS under license with ANSINot for ResaleNo reproduction or networking permitted without license from IHS-,-,-ANSI INCITS 370-2004 10 6.6.1.1 Programming Interface Code Table 4 defines the us

49、age and values of the Programming and Interface Byte. Table 4 PCI Adapter bit definitions in Programming Interface Byte Bit Read/write Description 0 Implementation dependent Determines the mode that the primary ATA channel is operating in. Clearing this bit to zero corresponds to compatibility, setting the bit to one means PCI-native mode. This bit is imp