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本文(ANSI ISO 8630-3-1987 Information processing - Data interchange on 130 mm (5.25 in) flexible disk cartridges using modified frequency modulation recording at 13 262 ftprad on 80 tra.pdf)为本站会员(roleaisle130)主动上传,麦多课文库仅提供信息存储空间,仅对用户上传内容的表现方式做保护处理,对上载内容本身不做任何修改或编辑。 若此文所含内容侵犯了您的版权或隐私,请立即通知麦多课文库(发送邮件至master@mydoc123.com或直接QQ联系客服),我们立即给予删除!

ANSI ISO 8630-3-1987 Information processing - Data interchange on 130 mm (5.25 in) flexible disk cartridges using modified frequency modulation recording at 13 262 ftprad on 80 tra.pdf

1、INTERNATIONAL STANDARD INTERNATIONAL ORGANIZATION FOR STANDARDIZATION ORGANISATION INTERNATIONALE DE NORMALISATION MEWYHAPQAHAR OPrAHbl3AMR I-IO CTAHAAPTH3Al. b) a flux transition shall be written at each cell boundary between consecutive bit cells containing ZEROS. Exceptions to this are defined in

2、 4.12. 4.2 Track location tolerance of the recorded flexible disk cartridge The centrelines of the recorded tracks shall be within f 0,042 5 mm (IL 0.001 67 in) of the nominal positions, over the range of operating environment specified in IS0 8636-l. 1 IS0 8630-3 : 1987 (E) 4.3 Recording offset ang

3、le At the instant of writing or reading a magnetic transition, the transition shall have an angle of O” f 18 with the radius. NOTE - As tracks may be written and overwritten at extremes of the tolerances given in 4.2 and 4.3, a band of old information may be left at one edge of the newly written dat

4、a and would constitute unwanted noise when reading. It is therefore necessary to trim the edges of the tracks by erasure after writing. 4.4 Density of recording 4.4.1 The nominal density of recording shall be 13 282 ftprad”. The resulting nominal bit cell length is 75.5 urad. 4.4.2 The long-term ave

5、rage bit cell length shall be the average bit cell length measured over a sector. It shall be within +I 3,0 % of the nominal bit cell length. 4.4.3 The short-term average bit cell length, referred to a par- ticular bit cell, shall be the average of the lengths of the preceding eight bit cells. It sh

6、all be within f 8 % of the long- term average bit cell length. 4.5 Flux transition spacing (see figure 1) The instantaneous spacing between flux transitions may be influenced by the reading and writing process, the bit sequence recorded (pulse crowding effects) and other factors. The locations of th

7、e transitions are defined as the locations of the peaks in the signal when reading. Tests should be carried out using a peak-sensing read amplifier (see annexes B and C). 4.5.1 The spacing between the flux ?ransitions in a sequence of ONES shall be between 80 % and 120 % of the short-term average bi

8、t cell length. 4.5.2 The spacing between the flux transition for a ONE and that between two ZEROS preceding or following it shall be between 130 % and 185 % of the short-term average bit cell length. 4.5.3 The spacing between the flux transitions of two ONES surrounding a ZERO shall lie between 185

9、% and 225 % of the short-term average bit cell length. 1 tl 1 1 rtl 0 4.6 Average Signal Amplitude For each side the Average Signal Amplitude on any track (see IS0 8530-l 1 of the interchanged flexible disk cartridge shall be less than 150 % of SRAIfand more than 40 % of SRAV. 4.7 Byte A byte is a g

10、roup of eight bit-positions, identified Bl to 88. The bit in each position is a ZERO or a ONE. 4.8 Sector All tracks shall be divided into 15 sectors of 512 bytes. 4.9 Cylinder A pair of tracks, one on each side of the disk, having the same track number. 4.10 Cylinder Number The Cylinder Number shal

11、l be a two-digit number identical with the track number of the tracks of the cylinder. 4.11 Data capacity of a track The data capacity of a track shall be 7 580 bytes. 4.12 Hexadecimal notation Hexadecimal notation shall be used hereafter to denote the following bytes : (00) for (B8 to Bl) = OOOWOOO

12、 (01) for (B8 to Bl) = 00000001 (02) for (B8 to Bl) = WOO0010 (4E) for (B8 to Bl) = 01001110 (FE) for (B8 to Bl) = 11111110 (FBI for (88 to Bl) = 11111011 (Al)” for (88 to Bl) = 101WOOl In byte (Al)” the boundary transition between B3 and 84 is missing. 0 1 n 0 1 130% to 165% 130%to 165% 185% to 225

13、% w Figure 1 l Flux transitions per radian 2 IS0 8530-3 : 1987 (El 4.13 Error Detection Characters (EDCI The two EDC bytes are hardware-generated by shifting serially the relevant bits, specified later for each part of the track, through a 16bit shift register described by the generator polynomial :

14、 Xl6 + X12 + X5 + 1 (See also annex A.) 5 Track layout After formatting, there shall be 15 usable sectors on each track. The layout of each track shall be as shown in figure 2. 5.1 Index Gap At nominal density, this field shall comprise not less than 32 bytes and not more than 146 bytes, the content

15、 of which is not specified except that it shall not contain an (Al Y-byte. Writing the Index Gap is started when the index hole is detected. Any of the first 16 bytes may become ill-defined due to subsequent overwriting. 5.2 Sector Identifier The layout of this field shall be as shown in table 1. Ta

16、ble 1 5.2.1 Identifier Mark This field shall comprise 16 bytes: 12 Ml)-bytes 3 (Al )*-bytes 1 (FELbyte 5.2.2 Address Identifier This field shall comprise 6 bytes. 5.2.2.1 Track Address This field shall comprise 2 bytes: a) Cylinder Number (Cl This field shall specify in binary notation the Cylinder

17、Number from 00 for the outermost cylinder to 79 for the innermost cylinder. b) Side Number (Side) This field shall specify the side of the disk. On side 0 it shall be (00) on all tracks. On side 1 it shall be (01) on all tracks. 5.2.2.2 Sector Number (S) The 3rd byte shall specify in binary notation

18、 the Sector Number from 01 for the first sector to 15 for the last sector. The sectors may be recorded in any order of their Sector Numbers. Identifier Mark Sector Identifier I Address Identifier Track Address S / EDC 12 bytes 3 bytes (OOI (Al)” 1 byte (FE) C Side 1 byte 1 byte 1 byte 1 byte (02) 2

19、bytes (00) or (01) INDEX GAP SECTOR IDENTIFIER IDENTIFIER 1st sector 15th sector Figure 2 IS0 6630-3 : 1967 (El 5.2.2.3 4th byte 5.5 Data Block Gap The 4th byte shall always be a (02Lbyte. 5.2.2.4 EDC This field shall comprise 84 initially recorded (4ELbytes. These bytes may have become ill-defined

20、due to overwriting. These two bytes shall be generated as defined in 4.13 using the bytes of the Sector Identifier starting with the first (Al )*-byte (see 5.2.1) of the Identifier Mark and ending with the 4th byte (see 5.2.2.3) of the Address Identifier. If the EDC is incorrect, then the sector is

21、defective. IS0 9293 specifies the handling of defective sectors. 5.3 identifier Gap The Data Block Gap is recorded after each Data Block and it precedes the following Sector Identifier. After the last Data Block, it precedes the Track Gap. 5.6 Track Gap This field shall follow the Data Block Gap of

22、the last sector. (4E)-bytes are written until the Index hole is detected, unless it has been detected during writing of the last Data Block Gap, in which case there shall be no Track Gap. This field shall comprise 22 initially recorded (4E)-bytes. 6 Coded representation of data These bytes may have

23、become ill-defined due to overwriting. 6.1 Standards 5.4 Data Block The layout of this field shall be as given in table 2. Table 2 fii The contents of the Data Field shall be recorded and inter- preted according to the relevant International Standards for the coding of information, for example IS0 6

24、46, IS0 2022 or IS0 4873. 6.2 Coding methods 6.2.1 When the coding method requires it, the Data Field shall be regarded as an ordered sequence of 8-bit bytes. 5.4.1 Data Mark This field shall comprise 16 bytes: 12 O)-bytes 3 (Al )*-bytes 1 (FBI-byte. Within each byte the bit positions shall be ident

25、ified by 88 to Bl. The high-order bit shall be recorded in position 88 and the low-order bit in position Bl . The sequence of recording shall be high-order bit first. When the data is encoded according to an 8-bit code, the binary weights of the bit positions shall be as shown in figure 3. 5.4.2 Dat

26、a Field This field shall comprise 512 bytes. Bit Position 88 87 B6 85 84 83 82 81 Binary Weights 128 64 32 16 8 4 2 1 If it comprises less than the requisite number of data bytes, the remaining positions shall be filled with UN-bytes. Figure 3 5.4.3 EDC These two bytes shall be generated as defined

27、in 4.13 using the bytes of the Data Block starting with the first (Al )*-byte of the Data Mark (see 5.4.1) and ending with the last byte of the Data When the data is encoded accordino to a 7-bit code, bit posi- tion B8 shall contain bit ZERO, and the data shall be encoded in bit positions 87 to Bl,

28、using the same binary weights as shown in figure 3. Field (see 5.4.2). If the EDC is incorrect, then the sector is defective. IS0 9293 specifies the handling of defective sectors. 6.2.2 When the coding method requires it, the Data Field shall be regarded as an ordered sequence of bit positions, each

29、 containing a bit. 4 IS0 8630-3 : 1987 (El Annex A EDC implementation (This annex does not form part of the standard.) Figure 4 shows the feedback connections of a shift register which may be used to generate the EDC bytes. Prior to operation, all positions of the shift register are set to ONE. Inpu

30、t data are added (exclusive OR) to the contents of position C15 of the register to form a feedback. This feedback is in its turn added (exclusive OR) to the contents of position C, and position C,. On shifting, the outputs of the exclusive OR gates are entered respectively into positions Cc, C5 and

31、C12. After the last data bit has been added, the register is shifted once more as specified above. The register then contains the EDC bytes. If further shifting is to take place during the writing of the EDC bytes, the control signal inhibits exclusive OR operations. To check for errors when reading

32、, the data bits are added into the shift register in exactly the same manner as they were during writing. After the data, the EDC bytes are also entered into the shift register as if they were data. After the final shift, the register con- tents will be all ZERO if the record does not contain errors

33、. Control - - with present technology only an analogue data separator based on a phase-locked oscillator can provide the necessary reliability. UDC 681327.63 Descriptors : data processing, information interchange, data recording devices, magnetic disks, flexible disks, track formats, specifications. Price based on 8 pages 8

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