ANSI JEDEC JS-001-2017 Electrostatic Discharge Sensitivity Testing Human Body Model (HBM) - Component Level.pdf

1、 ANSI/ESDA/JEDEC JS-001-2017 Revision of ANSI/ESDA/JEDEC JS-001-2014 For Electrostatic Discharge Sensitivity Testing Human Body Model (HBM) - Component Level EOS/ESD Association, Inc. 7900 Turin Road, Bldg. 3 Rome, NY 13440 JEDEC Solid State Technology Association 3103 North 10th Street Arlington, V

2、A 22201 An American National Standard Approved May 12, 2017 ANSI/ESDA/JEDEC JS-001-2017 ESDA/JEDEC Joint Standard for Electrostatic Discharge Sensitivity Testing - Human Body Model (HBM) - Component Level Approved December 8, 2016 EOS/ESD Association, Inc. ) are considered to be synonyms. In this do

3、cument the term “pin” is used to represent any device pin, land, bump, ball, or die pad. above-passivation layer (APL). A low-impedance metal plane, built on the surface of a die above the passivation layer that connects a group of bumps or pins (typically power or ground). NOTE: This structure is s

4、ometimes referred to as a redistribution layer (RDL). There may be multiple APLs (sometimes referred to as islands) for a power or ground group. associated non-supply pin. A non-supply pin (typically an input, output or I/O pin) is associated with a supply pin group if either: 1 EOS/ESD Association,

5、 Inc., 7900 Turin Road, Bldg. 3, Rome, NY 13440; Ph: 315-339-6937; www.esda.org 2 JEDEC, 3103 North 10th Street, Arlington, VA 22201; Ph: 703-907-7534; FAX: 703-907-7534; www.jedec.org ANSI/ESDA/JEDEC JS-001-2017 2 the current from the supply pin group (i.e., VDDIO) is required for the function of t

6、he electrical circuit(s) (I/O driver) that connect (high/low impedance) to that non-supply pin; or a parasitic path exists between non-supply and supply pin group (e.g., open-drain type non-supply pin to a VCC supply pin group that connects to a nearby N-well guard ring). cloned non-supply (IO) pin.

7、 Any of a set of input, output, or bidirectional pins using the same IO cell and electrical schematic and sharing the same associated supply pin group(s) including ESD power clamp(s). component. An item such as a resistor, diode, transistor, integrated circuit or hybrid circuit. NOTE: A component ma

8、y also be referred to as a device. component failure. A condition in which a tested component does not meet one or more specified static or dynamic data sheet parameters. coupled non-supply pin pair. Two pins, such as differential amplifier inputs, or low-voltage differential signaling (LVDS) pins,

9、that have between them an intended direct current path, such as a pass gate or resistor. NOTE: These pairs include analog and digital differential pairs and other special function pairs (e.g., D+/D-, XTALin/XTALout, RFin/RFout, TxP/TxN, RxP/RxN, CCP_DP/CCN_DN etc.). data sheet parameter. Any of the

10、static and dynamic component performance data supplied by the component manufacturer or supplier in a data sheet or other product specification. dynamic parameter. A parameter measured with the component in an operating condition. NOTE: These may include, but are not limited to full functionality, o

11、utput rise and fall times under a specified load condition, and dynamic current consumption. ESD withstand voltage; withstand threshold. The highest voltage level that does not cause device failure with the device passing all tests performed at lower voltages. NOTE: See note under “failure window” d

12、efinition. exposed pad. An exposed metal plate on an IC package, connected to the silicon substrate and acting as a heat sink. NOTE 1: This metal plate may or may not be electrically connected to the die. NOTE 2: The exposed pad may be categorized as either supply, non-supply or no-connect. failure

13、window. An intermediate range of stress conditions that can induce failure in a particular device type while the device type can pass some stress conditions both higher and lower than this range. NOTE: For example, a component with a failure window may pass a 500-volt test, fail a 1000-volt test and

14、 pass a 2000-volt test. Hence, the failure window of the device is between 500 volts and 2000 volts. The withstand voltage of this device is 500 volts. feedthrough. A direct or indirect (via a series resistor) connection from a pad cell layout that can allow additional elements, not included in the

15、pad cell, to make electrical connections to the bond pad. (See Annex G.) NOTE: This is not to be confused with the term feedthrough used in Section 5.0 which refers to test boards. HBM ESD tester; HBM simulator. Equipment that applies a human body model (HBM) ESD to a component. NOTE: This equipment

16、 is also referred to as “tester” in this standard. human body model (HBM) ESD. An electrostatic discharge (ESD) event meeting the waveform criteria specified in this standard, approximating the discharge from the fingertip of a typical human being to a grounded device. Ips (peak current value). The

17、current value determined by linear extrapolation of the exponential current decay curve back to the time (tmax) when the current actually peaked (Ipsmax). NOTE: The linear extrapolation should be based on the current waveform data over a 40-nanosecond period beginning at tmax. (See Figure 2A.) Ipsma

18、x (peak current maximum value). The highest current value measured. NOTE: This value includes the overshoot or ringing components due to internal test simulator RLC parasitics. (See Figure 2A.) ANSI/ESDA/JEDEC JS-001-2017 3 no-connect pin. A package interconnect (pin, bump, or ball) that is not elec

19、trically connected to a die. NOTE: In practice, there are some pins that are labeled as “no-connect”, but that are actually connected to the die and, therefore, should not be classified as a no-connect pins for the purpose of ESD testing. non-socketed tester. An HBM simulator that makes contact to t

20、he device under test (DUT) pins (or balls, lands, bumps, or die pads) with test probes rather than placing the DUT in a socket. non-supply pin. A pin that is not categorized as a supply pin or a no-connect. NOTE: Non-supply pins include pins such as input, output, offset adjusts, compensation, clock

21、s, controls, address, data, Vref pins and VPP pins on EPROM memory. Most non-supply pins transmit or receive information such as digital or analog signals, timing, clock signals, and voltage or current reference levels. package plane. A low-impedance metal layer built into an IC package connecting a

22、 group of bumps or pins (typically power or ground). There may be multiple package planes (sometimes referred to as islands) for each power and ground group. pre-pulse voltage. A voltage occurring at the device under test (DUT) just prior to the generation of the HBM current pulse. (See Annex B.2.)

23、pulse generation circuit. The circuit network that produces a human body discharge current waveform. NOTE: The circuit network includes a pulse generator with its test equipment internal path up to the contact pad of the test fixture. NOTE: This circuit is also referred to as a dual-polarity pulse s

24、ource. ringing. A high-frequency oscillation superimposed on a waveform. shorted non-supply pin. Any non-supply pin (typically an input, output or I/O pin) that is metallically connected (typically 3 ohm) on the chip or within the package to another non-supply pin (or set of non-supply pins). socket

25、ed tester. A simulator that makes contact to DUT pins (or balls, lands, bumps, or die pads) using a DUT socket mounted on a test fixture board. specification limit (SPL). The HBM limit value set by customer requirement or internal target. (See Annex G.) spurious current pulse. A small HBM shaped pul

26、se that follows the main current pulse and is typically defined as a percentage of Ipsmax. supply pin. Any device pin that provides operating current to that device. NOTE: Supply pins typically transmit no information (such as digital or analog signals, timing, clock signals, and voltage or current

27、reference levels). For the purpose of ESD testing, power and ground pins are treated as supply pins. static parameter. A parameter measured with the component in a non-operating condition. NOTE: Static parameters may include, but are not limited to, input leakage current, input breakdown voltage, ou

28、tput high and low voltages, output drive current, and supply current. step-stress-test hardening. The process of increasing the ESD withstand threshold by applying stress incrementally from low voltage to higher values. NOTE: This hardening occurs when a component subjected to increasing ESD voltage

29、 step-stresses is able to withstand higher stress levels than when another component expected to have the same threshold is evaluated using no step-stressing. NOTE: For example: a component may fail at 1000 volts if subjected to a single stress, but fail at 3000 volts if stressed incrementally from

30、250 volts. test fixture board. A specialized circuit board, with one or more component sockets, that connects the DUT(s) to the HBM simulator. tmax. The time when the current is at its maximum value (Ipsmax). (See Figure 2A.) trailing current pulse. A current pulse that occurs after the HBM current

31、pulse has decayed. (See Annex B.1.) NOTE: A trailing current pulse is a relatively constant current often lasting for hundreds of microseconds. ANSI/ESDA/JEDEC JS-001-2017 4 two-pin tester. A low-parasitic HBM simulator that tests DUTs in pin pairs in which floating pins are not connected to the sim

32、ulator, thereby eliminating DUT-tester interactions from parasitic tester loading of floating pins. V1. The maximum HBM stress voltage step at which all of the selected cloned non-supply pins pass. (See Annex G.) V2. The minimum HBM stress voltage step at which all the selected cloned non-supply pin

33、s fail. (See Annex G.) VM. The minimum HBM stress voltage step at which 50% or greater of the selected cloned non-supply pins fail. (See Annex G.) 4.0 APPARATUS AND REQUIRED EQUIPMENT 4.1 Waveform Verification Equipment All equipment used to evaluate the tester shall be calibrated in accordance with

34、 the manufacturers recommendation. This includes the oscilloscope, current transducer and high-voltage resistor load. Maximum time between calibrations shall be one year. Calibration shall be traceable to national standards, such as the National Institute of Standards and Technology (NIST) in the Un

35、ited States, or comparable international standards. Equipment capable of verifying the pulse waveforms defined in this standard test method includes, but is not limited to, an oscilloscope, evaluation loads and a current transducer. 4.1.1 Oscilloscope A digital oscilloscope is recommended but analog

36、 oscilloscopes are also permitted. In order to insure accurate current waveform capture, the oscilloscope shall meet the following requirements: a. Minimum sensitivity of 100 milliamperes per major division when used in conjunction with the current transducer specified in Section 4.1.2. b. Minimum b

37、andwidth of 350 MHz. c. For analog scopes, minimum writing rate of one major division per nanosecond. 4.1.1.1 Additional Requirements for Digital Oscilloscopes a. Recommended channels: 2 or more b. Minimum sampling rate: 1 GS/s c. Minimum vertical resolution: 8-bit d. Minimum vertical accuracy: + 2.

38、5% e. Minimum time base accuracy: 0.01% f. Minimum record length: 10 k points 4.1.2 Current Transducer (Inductive Current Probe) a. Minimum bandwidth of 200 MHz. b. Peak pulse capability of 12 amperes. c. Rise time of less than 1 nanosecond. d. Capable of accepting a solid conductor as specified in

39、Section 4.1.3. e. Provides an output voltage per signal current as required in Section 4.1.1. (This is usually between 1 and 5 millivolts per milliampere.) f. Low-frequency 3-dB-point below 10 kHz (e.g., Tektronix CT2) for measurement of decay constant td (see Section 5.2.3.1, Table 1, and note belo

40、w). NOTE: Results using a current probe with a low-frequency 3-dB-point of 25 kHz (e.g., Tektronix CT1) to measure decay constant td are acceptable if td is found to be between 130 and 165 nanoseconds. ANSI/ESDA/JEDEC JS-001-2017 5 4.1.3 Evaluation Loads Two evaluation loads are necessary to verify

41、tester functionality: a. Load 1: A solid 18-24 AWG (non-US standard wire size 0.25 to 0.75 mm2 cross-section) tinned copper shorting wire as short as practicable to span the distance between the two farthest pins in the socket while passing through the current probe or long enough to pass through th

42、e current probe and contacted by the probes of a non-socketed tester. b. Load 2: 500 ohms, 1%, minimum 4000-volt rating. 4.1.4 Attenuator A 20.0 dB attenuator with a precision of 0.5 dB, at least 1 GHz bandwidth, and an impedance of 50 ohms 5 ohms. 4.2 Human Body Model Simulator A simplified schemat

43、ic of the HBM simulator or tester is given in Figure 1. The performance of the tester is influenced by parasitic capacitance and inductance. Thus, construction of a tester using this schematic does not guarantee that it will provide the HBM pulse required for this standard. The waveform capture proc

44、edures and requirements described in Section 5.0 determine the acceptability of the equipment for use. Figure 1: Simplified HBM Simulator Circuit with Loads NOTES: 1. The current transducers (current probes) are specified in Section 4.1.2. 2. The shorting wire (Short) and 500-ohm resistor (R4) are e

45、valuation loads specified in Section 4.1.3. 3. Reversal of Terminals A and B to achieve dual polarity performance is not permitted except under conditions described in, Sections 6.5.1.3 and 6.6. 4. The charge removal circuit ensures a slow discharge of the device, thus avoiding the possibility of a

46、charged device model discharge. A simple example is a 10-kilohm or larger resistor (possibly in series with a switch) in parallel with the test fixture board. This resistor may also be useful to control parasitic pre-pulse voltages (See Annex B.2). 5. The dual polarity pulse source (generator) shall

47、 be designed to avoid recharge transients and double pulses. 6. Stacking of DUT socket adapters (piggybacking or the insertion of secondary sockets into the main test socket) is allowed only if the secondary socket waveform meets the requirements of this standard defined in Table 1. 7. Component val

48、ues are nominal. ANSI/ESDA/JEDEC JS-001-2017 6 4.2.1 HBM Test Equipment Parasitic Properties Some HBM simulators have been found to falsely classify HBM sensitivity levels due to parasitic artifacts or uncontrolled voltages unintentionally built into the HBM simulators. Methods for determining if th

49、ese effects are present and optional mitigation techniques are described in Annex B. Two-pin testers and non-socketed testers may have smaller parasitic capacitances and may reduce the effects of tester parasitics by contacting only the pins being stressed. 5.0 STRESS TEST EQUIPMENT QUALIFICATION AND ROUTINE VERIFICATION 5.1 Overview of Required HBM Tester Evaluations The HBM tester and test fixture boards shall be qualified, re-qualified, and periodically verified as described in this section. A flow chart for this procedure is given in Annex A. The safety precautions described in