ANSI SP14.5-2015 Near-Field Immunity Scanning - Component Module PCB Level.pdf

1、 For Electrostatic Discharge Sensitivity Testing Near-Field Immunity Scanning - Component/Module/PCB Level Electrostatic Discharge Association 7900 Turin Road, Bldg. 3 Rome, NY 13440 An American National Standard Approved September 14, 2015 ANSI/ESD SP14.5-2015 ESD Association Standard Practice for

2、Electrostatic Discharge Sensitivity Testing Component/Module/PCB Level Approved August 21, 2015 ESD Association ANSI/ESD SP14.5-2015 Electrostatic Discharge Association (ESDA) standards and publications are designed to serve the public interest by eliminating misunderstandings between manufacturers

3、and purchasers, facilitating the interchangeability and improvement of products and assisting the purchaser in selecting and obtaining the proper product for his particular needs. The existence of such standards and publications shall not in any respect preclude any member or non-member of the Assoc

4、iation from manufacturing or selling products not conforming to such standards and publications. Nor shall the fact that a standard or publication that is published by the Association preclude its voluntary use by non-members of the Association whether the document is to be used either domestically

5、or internationally. Recommended standards and publications are adopted by the ESDA in accordance with the ANSI Patent policy. Interpretation of ESDA Standards: The interpretation of standards in-so-far as it may relate to a specific product or manufacturer is a proper matter for the individual compa

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12、 7900 Turin Road, Bldg. 3 Rome, NY 13440 Copyright 2015 by ESD Association All rights reserved No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without the prior written permission of the publisher. Printed in the United States of America ISB

13、N: 1-58537-284-6 DISCLAIMER OF WARRANTIES DISCLAIMER OF GUARANTY LIMITATION ON ESDAs LIABILITY CAUTION NOTICE ANSI/ESD SP14.5-2015 i (This foreword is not part of ESD Association Standard Practice ANSI/ESD SP14.5-2015.) FOREWORD One of the biggest problems when ESD testing a functional system or sub

14、-system is the analysis of unacceptable soft-errors, upsets, bit errors and similar faults that occur during ESD testing. These failures are also referred to as “soft” failures, which are non-destructive and the unit being tested works fine when re-set or re-booted. Following a “soft” failure, no ph

15、ysical evidence exists to allow troubleshooting using traditional methods. Scanning as described in this document provides a method of identifying areas, traces, and individual devices sensitive to ESD therefore providing engineers with key information to deduce the causes of “soft” failures. Knowin

16、g the failure and specific areas sensitive to the ESD event allows the engineer to apply product/circuit knowledge to identify root cause and correct the problem. This standard practice1 defines a test method for evaluating the sensitivity of ICs, modules or boards for susceptibility to field-couple

17、d impulsive disturbances. The main focus lies on soft-errors, i.e., upsets, bit errors etc. The field-coupled disturbance is derived from measured field pulses as they can occur inside a system subjected to human-metal ESD, as it is defined by the IEC 61000-4-2 system level ESD test standard. The mo

18、tivation for using near-field immunity scanning is to determine the robustness of ICs, modules or PCBs is fivefold: Localizing sensitive areas. While the system level standard allows one to determine if a system is passing or failing, it does not identify the root cause of an ESD sensitivity. Root-c

19、ause analysis is best done with near-field immunity scanning. Repeatability. The problems of repeatability of system level testing are well publicized and near field scanning has been shown to offer much better reproducibility in determining ESD sensitivities. Relative characterization at the module

20、 level. System level testing requires having a complete, operational system, but using near-field scanning allows one to determine the sensitivity of individual modules against ESD-like pulses. Relative characterization at the IC level. Many ESD problems, especially in hand-held products, are not ca

21、used by coupling into the PCB, but rather by direct coupling into the ICs. Using a near-field scanning system, one can determine the sensitivity of an IC to electric or magnetic field coupling. Fulfillment of system level requirements. Using near-field scanning techniques, one can compare the sensit

22、ivities of previous and new models, and in many cases obtain good indications of robustness without retesting the complete system. This test method is not a substitute for system-level testing but compliments it by providing a tool for identifying problem areas. This standard practice was designated

23、 ANSI/ESD SP14.5-2015 and approved on August 21, 2015. 1 ESD Association Standard Practice (SP): A procedure for performing one or more operations or functions that may or may not yield a test result. Note, if a test result is obtained it is not reproducible. ANSI/ESD SP14.5-2015 ii At the time ANSI

24、/ESD SP14.5-2015 was prepared, the 14.0 System Level ESD Subcommittee had the following members: Thomas Meuse, Chair Thermo Fisher Scientific Robert Ashton ON Semiconductor Jon Barth Barth Electronics, Inc. Fabrice Caignet LAAS-CNRS Lorenzo Cerati STMicroelectronics Jeffrey Dunnihoo Pragma Designs R

25、einhold Gaertner Infineon Technologies Horst Gieser Fraunhofer EMFT Vaughn Gross Green Mountain ESD Labs, LLC Evan Grund Grund Technical Solutions, LLC Leo G. Henry ESD/TLP Consultants Michael Hopkins Hopkins Technical Timothy Maloney Intel Corporation Gene Monroe NASA LARC Paul Phillips Phasix ESD

26、Bill Reynolds IBM Alan Righter Analog Devices, Inc. David Rose Semtech Corporation Masanori Sawada Hanwa Electronic Ind. Co., Ltd. Wolfgang Stadler Intel Mobile Communications Steven Voldman Dr. Steven H. Voldman, LLC Scott Ward Texas Instruments The following individuals made significant contributi

27、ons to ANSI/ESD SP14.5-2015: Moon Lee Semtech Corporation Leo Luquette Cypress Semiconductor Kyungjin Min Amber Precision Instruments Kathleen Muhonen Qorvo, Inc. Nathaniel Peachey Qorvo, Inc. David Pommerenke Missouri University of Science and Technology Mirko Scholz IMEC vzw Belgium Karen Shrier E

28、lectronic Polymers Newco, Inc. ANSI/ESD SP14.5-2015 iii TABLE OF CONTENTS 1.0 PURPOSE AND SCOPE . 1 1.1 PURPOSE . 1 1.2 SCOPE . 1 2.0 REFERENCED PUBLICATIONS 1 3.0 DEFINITIONS 1 4.0 PERSONNEL SAFETY . 1 5.0 EQUIPMENT . 2 5.1 SCANNING SYSTEM . 2 5.2 PULSE SOURCE / TRANSMISSION LINE PULSER. 3 5.3 PROB

29、ES . 3 6.0 WAVEFORM . 3 6.1 PULSE GENERATION REQUIREMENTS . 4 7.0 TEST SETUP 4 7.1 TEST SETUP OVERVIEW 4 7.2 TEST PARAMETERS . 5 7.2.1 Scan Area . 5 7.2.2 Point Density . 6 7.2.3 Field Probe Type . 6 7.2.4 Field Probe Orientation . 6 7.2.5 Pulse Polarity 6 7.2.6 Pulse Rate and Number of Pulses per T

30、est Point 6 7.3 DUT COMMUNICATION 6 7.4 TEST SYSTEM VERIFICATION . 7 7.5 TEST STRATEGIES 7 7.6 DATA STORAGE FORMAT . 9 8.0 RECOMMENDED TEST LEVELS 9 9.0 DISTURBANCE CRITERIA 9 10.0 DOCUMENTATION . 10 ANSI/ESD SP14.5-2015 iv ANNEXES Annex A (Informative): Waveform Verification . 11 Annex B (Informati

31、ve): Field Coupling 19 Annex C (Informative): Data Visualization 22 Annex D (Informative): Bibliography . 25 TABLES Table 1: General Waveform Parameters 4 Table 2: Recommended Test Levels 9 Table 3: Geometry Parameters for the Microstrip Trace 11 Table 4: Voltage Induced at Each End of a 20 mm (0.79

32、 inch) Trace . 20 FIGURES Figure 1: Principle Representation of the Voltage Induced by the Suggested Transmission Line Pulser Pulse in Case of Electric Field Coupling 4 Figure 2: Main Components of a Typical Immunity Scanning System . 5 Figure 3: Generic Flow Diagram for Scan Test 8 Figure 4: Micros

33、trip Trace for Capturing the Induced Voltages 12 Figure 5: Rising Edge of the TLP Waveform 13 Figure 6: Schematic of the Test Set-up to Capture the Coupled Waveforms at the Trace Ports 14 Figure 7: 5 mm (0.20 inch) Hx Probe Mounted over the Center of the Trace 14 Figure 8: Induced Voltage from the E

34、z Probe 1 mm (0.039 inch) above Trace, 1 kV TLP Charge Voltage 15 Figure 9: Sum and Differential Voltages Caused by the Ez Probe 1 mm (0.039 inch) above the Trace, 1 kV TLP Charge Voltage . 15 Figure 10: Induced Voltage from the Hx Probe 1 mm (0.039 inch) above Trace, 1 kV TLP Charge Voltage 16 Figu

35、re 11: Induced Voltage from an Hz Probe, Zoffset= 1 mm (0.039 inch), Xoffset= 4.21 mm (0.165 inch), 1 kV TLP Charge Voltage 16 Figure 12: Induced Voltage from the Ez Probe 5 mm (0.20 inch) above Trace, 1 kV TLP Charge Voltage 17 Figure 13: Sum and Differential Voltage Induced by the Hz Probe, Zoffse

36、t = 5 mm (0.20 inch), Xoffset = 4.21 mm (0.165 inch), 1 kV TLP Charge Voltage . 17 Figure 14: Illustration of the Electric Field Coupling and its Return Current Flow 19 Figure 15: Illustration of the Magnetic Field Caused by a Horizontal Loop Close to a Ground Plane 20 Figure 16: Voltage Induced in

37、the Trace when H-probe is offset by 3.5 mm (0.14 inch); Monitored at Both Trace Terminations 21 Figure 17: Comparison of Two Functionally Identical ICs from Different Vendors 23 Figure 18: Identification of Sensitive Traces Close to a Microprocessor using Immunity Scanning 23 Figure 19: Electric Fie

38、ld and Magnetic Field Sensitivity of an LCD 24 ESD Association Standard Practice ANSI/ESD SP14.5-2015 1 ESD Association Standard Practice for Electrostatic Discharge Sensitivity Testing Near Field Immunity Scanning - Component/Module/PCB Level 1.0 PURPOSE AND SCOPE 1.1 Purpose The purpose of this st

39、andard practice is to establish a test method for immunity scanning of ICs, modules and PCBs. Results from scanning relate to the system level performance but cannot be used to predict system level performance using the IEC 61000-4-2 test method. The reason is that variations exist in coupling paths

40、 between injection points and local current densities and associated fields coupled into traces or ICs. This standard practice addresses testing of ICs, modules, and PCBs under powered conditions. This test method focuses on soft errors, such as bit errors and upsets, keeping in mind that fast pulse

41、s can also cause latch-up. Use of the standard practice will guide the user in the identification of the root causes of electrostatic discharge (ESD) induced soft errors in ICs, modules, and PCBs, for debugging and quality control purposes. 1.2 Scope This standard practice establishes the procedure

42、for testing and characterizing the sensitivity of ICs, modules, and PCBs against the effect of field-coupled pulses that are generated by ESD type pulses. The field-coupled pulses derived from the fast leading edge of transmission line pulses closely resemble electromagnetic fields as they occur ins

43、ide a product subjected to human-metal ESD, such as specified by the IEC 61000-4-2. IEC 61000-4-2 is the primary standard for system level ESD test standard. 2.0 REFERENCED PUBLICATIONS Unless otherwise specified, the following documents of the latest issue, revision or amendment form a part of this

44、 standard practice to the extent specified herein: IEC 61000-4-2, Electromagnetic Compatibility (EMC) Part 4.2: Testing and Measurement Techniques Electrostatic Discharge Immunity2 IEC/TR 61967-1-1, Integrated circuits - Measurement of electromagnetic emissions - Part 1-1: General conditions and def

45、initions - Near-field scan data exchange format2 3.0 DEFINITIONS The terms used in the body of this document are in accordance with the definitions found in ESD ADV1.0, ESD Associations Glossary of Terms available for complimentary download at www.esda.org. 4.0 PERSONNEL SAFETY THE PROCEDURES AND EQ

46、UIPMENT DESCRIBED IN THIS STANDARD PRACTICE MAY EXPOSE PERSONNEL TO HAZARDOUS ELECTRICAL CONDITIONS. USERS OF THIS STANDARD PRACTICE ARE RESPONSIBLE FOR SELECTING EQUIPMENT THAT 2 International Electrotechnical Commission; 3, rue de Varemb, CH - 1211 GENEVA 20, Switzerland; www.iec.ch ANSI/ESD SP14.

47、5-2015 2 COMPLIES WITH APPLICABLE LAWS, REGULATORY CODES AND BOTH EXTERNAL AND INTERNAL POLICY. USERS ARE CAUTIONED THAT THIS DOCUMENT CANNOT REPLACE OR SUPERSEDE ANY REQUIREMENTS FOR PERSONNEL SAFETY. GROUND FAULT CIRCUIT INTERRUPTERS (GFCI) AND OTHER SAFETY PROTECTION SHOULD BE CONSIDERED WHEREVER

48、 PERSONNEL MIGHT COME INTO CONTACT WITH ELECTRICAL SOURCES. ELECTRICAL HAZARD REDUCTION PRACTICES SHOULD BE EXERCISED AND PROPER GROUNDING INSTRUCTIONS FOR EQUIPMENT SHALL BE FOLLOWED. THE RESISTANCE MEASUREMENTS OBTAINED THROUGH THE USE OF THIS TEST METHOD SHALL NOT BE USED TO DETERMINE THE RELATIV

49、E SAFETY OF PERSONNEL EXPOSED TO HIGH AC OR DC VOLTAGES. SCANNING SYSTEMS MOVE PROBES, THUS, CARE SHOULD BE TAKEN TO AVOID INJURIES FROM THESE POWERFUL MOTOR DRIVEN DEVICES. ANOTHER POTENTIAL RISK ARISES FROM THE HIGH VOLTAGE SUPPLIES. MOST TRANSMISSION LINE PULSERS HAVE VOLTAGES OF 8 KILOVOLT OR LESS AND CHARGE CABLES OF TYPICALLY UP TO 10 M IN LENGTH. THIS LEADS TO ABOUT 1 NF CAPACITANCE AT 8 KILOVOLT, CARE NEEDS TO BE TAKEN NOT TO COME IN CONTACT WITH THE TLP GENERATED VOLTAGE. 5.0 EQUIPMENT All equipment within the test system must be able to w