ANSI SP5.6-2009 Electrostatic Discharge Sensitivity Testing C Human Metal Model (HMM) - Component Level.pdf

1、 ANSI/ESD SP5.6-2009 For Electrostatic Discharge Sensitivity Testing Human Metal Model (HMM) - Component Level Electrostatic Discharge Association 7900 Turin Road, Bldg. 3 Rome, NY 13440 An American National Standard Approved January 6, 2010 ANSI/ESD SP5.6-2009 ESD Association Standard Practice for

2、Electrostatic Discharge Sensitivity Testing Human Metal Model (HMM) Component Level Approved September 16, 2009 ESD Association ANSI/ESD SP5.6-2009 Electrostatic Discharge Association (ESDA) standards and publications are designed to serve the public interest by eliminating misunderstandings between

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5、estically or internationally. Recommended standards and publications are adopted by the ESDA in accordance with the ANSI Patent policy. Interpretation of ESDA Standards: The interpretation of standards in-so-far as it may relate to a specific product or manufacturer is a proper matter for the indivi

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12、on 7900 Turin Road, Bldg. 3 Rome, NY 13440 Copyright 2010 by ESD Association All rights reserved No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without the prior written permission of the publisher. Printed in the United States of America I

13、SBN: 1-58537-166-1 CAUTION NOTICE DISCLAIMER OF WARRANTIES DISCLAIMER OF GUARANTY LIMITATION ON ESDAs LIABILITY ANSI/ESD SP5.6-2009 i (This foreword is not part of ESD Association Standard Practice ANSI/ESD SP5.6-2009) FOREWORD This standard practice1defines two methods for generating and applying s

14、tress pulses as part of the evaluation of electrical component sensitivity to electrostatic discharge. The name Human Metal Model (HMM) is derived from the anticipated ESD stress that could be generated from a person holding a metal tool. The current pulse delivered to the component in this test is

15、intentionally the same pulse as defined in the IEC 61000-4-2 testing method. Customers of IC manufacturers have begun requesting that ICs be evaluated for their ability to withstand the IEC 61000-4-2 stress pulses. However, because this IEC specification only describes testing a complete system, tha

16、t specification cannot be directly applied to devices such as ICs and discrete components. This document attempts to provide IC manufacturers and IC customers with testing methods applicable to devices that utilize the current waveform of IEC 61000-4-2. The technique described in this document is te

17、rmed “Human Metal Model” testing to differentiate it from the system level IEC 61000-4-2. Many companies have developed their own testing techniques using IEC 61000-4-2 pulses from hand-held gun generators for device and circuit design evaluation. This technique or practice is being utilized on prod

18、ucts in packaged configurations. Development of the HMM Standard Practice is in response to the need of the industry for consistent testing methods. ESD testing of devices and components has become standard for qualification of parts. Device level ESD testing is only intended to be applicable to ele

19、ctrostatic events occurring up to final assembly of the system or consumer product. System level testing has then been performed to verify that adequate protection is present to withstand typical electrostatic stresses in the field. Recently, some system manufacturers have begun requiring system lev

20、el testing to be done on devices before designing them into the final product. This is being done under the assumption that system level test results from devices or components should be directly applicable to the results of these same components in the final system. While it may be prudent to requi

21、re some level of testing on devices, modules, or components that are connected to external ports, merely using a system level test for these devices can yield ambiguous results. Without a full description of the test setup during stress the amount of stress current delivered to the component under s

22、tress testing can vary dramatically between different laboratories performing the test. Another source of ambiguity comes from the effect of the electromagnetic (EM) field radiated from an ESD gun designed for system level testing. In a system, individual devices and components are afforded at least

23、 a certain amount of shielding by the packaging of the system. This is not present in the stand-alone device or component. Thus the EM field generated during a contact discharge ESD gun event can interact with the traces, connections and circuits much more directly and may cause false failures. Clea

24、rly, a method of testing is required that can deliver the types of stresses the component will experience in the final product in a manner that is systematic and controlled. This standard practice seeks to do this by providing the user with instructions for producing two test methods that should all

25、ow repeatable IEC stress to devices. To eliminate excess gun radiation from IEC device testing, the same waveform can be generated by a stationary source. It is delivered through a 50 ohm coaxial cable to the test board holding the CUT or device under test (DUT). Test methods and specifications for

26、this alternative method are included. This standard practice addresses testing of components in both powered and un-powered conditions. Use of the standard practice will result in devices, modules and components being tested in a more consistent fashion and in a better controlled environment than th

27、ey would be using an unmodified system level test procedure. This document defines a standard practice to be used in the semiconductor industry for HMM testing in both industrial and academic 1ESD Association Standard Practice (SP): A procedure for performing one or more operations or functions that

28、 may or may not yield a test result. Note, if a test result is obtained it is not reproducible. ANSI/ESD SP5.6-2009 ii institutions. (This document is intended to be used by electrical technicians, electrical engineers, semiconductor process and device engineers, system engineers, ESD reliability an

29、d quality engineers, and circuit designers.) The document is to act as an educational guide, a learning document, and as a reference for the practices being used today. The values stated in the document are guidelines, not specifications. The values stated are the majority consensus of the contribut

30、ors from both industry and academic environments. The context of this document is the application of HMM techniques for the electrical characterization of components. These components can be single devices, a plurality of devices, integrated circuits, or semiconductor chips. This methodology is rele

31、vant to both active and passive elements. This test method is applicable to diodes, MOSFET devices, bipolar transistors, resistors, capacitors, inductors, and related components. The IEC gun contact discharge mode test method is described in this standard practice because it provides more repeatable

32、 pulses than the air discharge mode. This standard practice was approved on September 16, 2009 and was designated ANSI/ESD SP5.6-2009. At the time ANSI/ESD SP5.6-2009 was prepared, the 5.6 Device Testing (HMM) Subcommittee had the following members: Nathaniel M. Peachey, Chairman RF Micro Devices (R

33、FMD) Robert Ashton ON Semiconductor, Inc. Jon Barth Barth Electronics, Inc. Aniket A. Breed Intel Corporation Marcel Dekker MASER Engineering BV Hani Geske Semtech Corporation Horst Gieser Fraunhofer IZM Vaughn Gross Green Mountain ESD Labs, LLC Evan Grund Grund Technical Solutions, LLC Leo G. Henry

34、 ESD-TLP Consultants Marcos Hernandez Thermo Fisher Scientific Mike Hopkins Amber Precision Instruments Larry Johnson LSI Corporation Leo Luquette Cypress Semiconductors Douglas J. Miller Sandia National Laboratories Kathy Muhonen Penn State University Erie, The Behrend College Chris OConnor Robson

35、Technologies, Inc. Alan Righter Analog Devices, Inc. (ADI) Mirko Scholz IMEC Karen Shrier Electronic Polymers, Inc. Wolfgang Stadler Infineon Technologies AG Hans van Zwol NXP Semiconductors Steven H. Voldman Dr. Steven H. Voldman, LLC Scott Ward Texas Instruments The following individuals made sign

36、ificant contributions to this document: Mike Chaine Micron Technology Marti Farris Intel Corporation Steve Marum Texas Instruments Tom Meuse Thermo Fisher Scientific Ravindra Narayan Theo Smedes NXP Semiconductors ANSI/ESD SP5.6-2009 iii TABLE OF CONTENTS 1.0 SCOPE AND PURPOSE1 1.1 SCOPE . 1 1.2 PUR

37、POSE . 1 2.0 REFERENCED PUBLICATIONS.1 3.0 DEFINITIONS.1 4.0 PERSONNEL SAFETY2 5.0 EQUIPMENT 2 5.1 CURRENT MEASUREMENT SYSTEM 2 5.2 ESD PULSE SOURCE 2 5.3 OHMMETER 3 5.4 VOLTMETER 3 6.0 WAVEFORM 3 6.1 PULSE GENERATION REQUIREMENTS. 3 7.0 TEST SETUP .4 7.1 TEST SETUP OVERVIEW 4 7.1.1 Test Setup A .4

38、7.1.2 Test Setup B .5 7.1.3 Test Setup C .5 8.0 TESTING AND WAVEFORM VERIFICATON .6 8.1 TEST PROCEDURE 6 8.2 WAVEFORM INTEGRITY MEASUREMENT PROCEDURE 7 8.2.1 Procedure for ESD Gun With Discharge Point Directly Connected to the Circuit Board Ground7 8.2.2 Procedure for ESD Gun With Discharge Point Co

39、nnected to Component Ground Pin7 8.2.3 Procedure for Waveform Verification With Test Setup C (see Section 7.1.3) 7 8.3 TEST BOARD DESCRIPTION . 8 8.3.1 Circuit Board .8 8.3.2 HMM 50 ohm Test Board10 8.4 UNPOWERED BOARD. 10 8.5 POWERED BOARD. 10 9.0 FAILURE CRITERIA11 9.1 DOCUMENTATION 11 ANSI/ESD SP

40、5.6-2009 iv ANNEX A (INFORMATIVE): HMM GENERAL GUIDANCE .13 A.1 THE EQUATION OF AN IDEALIZED WAVEFORM INTO A 2 OHM LOAD . 13 A.2 PULSED DELIVERY SYSTEM USING A SHIELDED CABLE 13 A.2.1 Background.13 A.2.2 Test Setup.14 A.2.3 Pulser Verification .14 A.2.4 TFB Verification.14 A.3 CURRENT PROBES 14 A.4

41、EXTENSION TO OTHER WAVEFORMS 17 A.5 VERIFYING STRESS APPLIED TO DUT 17 A.6 INFORMATIVE REFERENCES. 18 FIGURES Figure 1: HMM Waveform Illustrating the Parameters Used to Define the Pulse . 4 Figure 2: Schematic of HMM Test Setup (Powered Board) 4 Figure 3: Test Setup A Diagram 5 Figure 4: Test Setup

42、B Diagram 5 Figure 5: Layout of IEC 50 ohm Coaxial Source Test Fixture Board 6 Figure 6: Example of Layout of IEC 50 ohm Coaxial Source Test Fixture Board (Power Source and Capacitors not Shown) 6 Figure 7: Layout of Circuit Board Showing Ground Connections (Power Source and Capacitors not Shown) 9

43、Figure 8: Physical Arrangement 15 Figure 9: Resulting Waveforms . 15 Figure 10: Simultaneous Measurement of Current Measurement using IEC Probe and F65-A. 16 Figure 11: Comparison of Fischer F65-A Probe with IEC Current Probe . 16 TABLES Table 1: General Waveform Parameters 3 Table 2: Human Metal Mo

44、del Pulse Parameters 3 Table 3: Recommended Test Levels 11 ESD Association Standard Practice ANSI/ESD SP5.6-2009 1 ESD Association Standard Practice for Electrostatic Discharge Sensitivity Testing Human Metal Model (HMM) Component Level 1.0 SCOPE AND PURPOSE 1.1 Scope This document establishes the p

45、rocedure for testing, and characterizing the electrostatic discharge (ESD) sensitivity of component pins that will be directly connected to external connectors or ports on a completed system. This method is not intended for ESD testing of device, module, or component pins that do not directly connec

46、t to a system port or connector. This document covers testing under un-powered and powered states but does not cover testing of integrated circuits in a functioning state. For the purposes of this document, the HMM test pulse will be modeled after the contact discharge defined by the IEC 61000-4-2 d

47、ocument. 1.2 Purpose The purpose of this document is to establish a test method for stressing pins of electrical components such as integrated circuits, protection elements, or filters that will be directly connected to external ports of a system and may be subjected to a system level type ESD stres

48、s waveform. This document is not intended to prove that a component will survive stress of a specified level within a completed system or to estimate the protection level from ESD that is incorporated within a system. Variations in system design, component level packaging and the individual part res

49、ponse to an ESD stress make such predictions impossible with a single test. The objective of this test is to provide a baseline for characterization of ESD protection on device pins prior to incorporation of those devices or components into the completed system. NOTE: Component testing to this procedure will not predict how the component will react to system level tests according to IEC 61000-4-2. 2.0 REFERENCED PUBLICATIONS Unless otherwise specified, the following documents of the latest issue, revision or amendment form a part of this standard to the extent s