ANSI TIA EIA 644-A-2001 Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits《低压差示信号接口电路的电性能》.pdf

1、 TIA/EIA STANDARD Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits TIA/EIA-644-A (Revision of TIA/EIA-644) FEBRUARY 2001 TELECOMMUNICATIONS INDUSTRY ASSOCIATION The Telecommunications Industry Association Represents the Communications Sector of ANSI/TIA/EIA-

2、644-A-2001 Approved: January 30, 2001 TIA/EIA-644-ACopyright Telecommunications Industry Association Provided by IHS under license with EIANot for ResaleNo reproduction or networking permitted without license from IHS-,-,-NOTICE TIA/EIA Engineering Standards and Publications are designed to serve th

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6、ume any obligation whatever to parties adopting the Standard or Publication. This Standard does not purport to address all safety problems associated with its use or all applicable regulatory requirements. It is the responsibility of the user of this Standard to establish appropriate safety and heal

7、th practices and to determine the applicability of regulatory limitations before its use. (From Standards Proposal No. 4584, formulated under the cognizance of the TIA TR-30.2 Subcommittee on DTE-DCE Interfaces Protocols.) Published by TELECOMMUNICATIONS INDUSTRY ASSOCIATION 2001 Standards and Techn

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12、ted without license from IHS-,-,-ELECTRICAL CHARACTERISTICS OF LOW VOLTAGE DIFFERENTIAL SIGNALING(LVDS) INTERFACE CIRCUITS(From TIA/EIA Standard TIA/EIA-644 and Standards ProposalNo. 4584 formulated under the cognizance of TIASubcommittee TR-30.2 on Data Transmission Interfaces and Protocols)Content

13、s Page1 SCOPE . 12 DEFINITIONS, SYMBOLS AND ABBREVIATIONS . 22.1 Data signaling rate 22.2 DTE. 22.3 DCE 22.4 LVDS 22.5 Star (*) 23 APPLICABILITY. 33.1 General applicability. 33.2 Data signaling rate 34 ELECTRICAL CHARACTERISTICS. 54.1 Generator characteristics. 54.1.1 Full load test measurements. 64

14、.1.2 Offset voltage and balance measurements 74.1.3 Short-circuit measurements. 84.1.4 Output signal waveform 84.1.5 Dynamic output signal balance 94.2 Load characteristics .104.2.1 Receiver input current - voltage measurements.114.2.2 Receiver input balance measurements 114.2.3 Terminating receiver

15、 input current - voltage measurements and inputimpedance measurements 124.2.4 Receiver input sensitivity measurements .144.2.5 Media termination.154.3 Interconnecting media electrical characteristics164.3.1 Cable media174.3.1.1 Maximum dc loop resistance (DCR):174.3.1.2 Characteristic impedance:.17C

16、opyright Telecommunications Industry Association Provided by IHS under license with EIANot for ResaleNo reproduction or networking permitted without license from IHS-,-,-TIA/EIA-644-Aii4.3.1.3 Additional parameters174.3.2 PC Board trace media .174.3.3 Other media.174.4 System parameters.174.4.1 Mult

17、iple receiver operation.174.4.2 Failsafe operation.194.4.3 Total load limit195 ENVIRONMENTAL CONSTRAINTS.206 CIRCUIT PROTECTION.217 OPTIONAL GROUNDING ARRANGEMENTS.227.1 Signal common (ground)227.1.1 Configuration “A“.227.1.2 Configuration “B“.237.2 Shield ground - cable applications23A.1 INTERCONNE

18、CTING CABLE24A.1.1 Length.24A.1.2 Typical cable characteristics25A.1.2.1 Parallel interface cable .25A.1.2.1.1 Parallel cable, physical characteristics25A.1.2.1.2 Parallel cable, electrical characteristics 25A.1.2.2 Serial interface cable26A.1.2.2.1 Serial cable, physical characteristics.26A.1.2.2.2

19、 Serial cable, electrical characteristics.26A.1.3 Cable termination26A.2 CABLE LENGTH VS. DATA SIGNALING RATE GUIDELINES.27B.1 COMPATIBILITY WITH OTHER INTERFACE STANDARDS.28B.1.1 Compatibility with IEEE 1596.3.28B.1.2 Inter-operation with other interface standards28B.2 RELATED TIA/EIA STANDARDS29B.

20、3 OTHER RELATED INTERFACE STANDARDS .29Copyright Telecommunications Industry Association Provided by IHS under license with EIANot for ResaleNo reproduction or networking permitted without license from IHS-,-,-TIA/EIA-644-AiiiFOREWORD(This foreword is not part of this Standard)This Standard was form

21、ulated under the cognizance of TIA Subcommittee TR-30.2 onData Transmission Interfaces.This Standard was developed in response to a demand from the data communicationscommunity for a general-purpose high-speed interface standard for use in high throughputDTE-DCE interfaces.The voltage levels specifi

22、ed in this Standard were specified such that maximum flexibilitywould be provided, while providing a low power, high speed, differential interface.Generator output characteristics are independent of power supply, and may be designedfor standard +5 V, +3.3 V or even power supplies as low as +2.5 V. I

23、ntegrated circuittechnology may be BiCMOS, CMOS, or GaAs technology. The low voltage (330 mV)swing limits power dissipation, while also reducing radiation of EMI signals. Differentialsignaling provides multiple benefits over single-ended signaling, notably common-moderejection, and magnetic cancelin

24、g.Additional specifications for multidrop applications have been incorporated into TIA/EIA-644-A. A full load test measurement for the generator and a balance test of receiver inputcurrent have been added to this revision. A survey of devices conforming to TIA/EIA-644currently available are able to

25、meet the additional requirements of TIA/EIA-644-A.This Standard includes two Annexes, both are informative only. Annex A providesguidelines for application, addressing data signaling rate and cable length issues. Annex Bprovides comparison information with other interface standards, and related stan

26、dards.Copyright Telecommunications Industry Association Provided by IHS under license with EIANot for ResaleNo reproduction or networking permitted without license from IHS-,-,-Copyright Telecommunications Industry Association Provided by IHS under license with EIANot for ResaleNo reproduction or ne

27、tworking permitted without license from IHS-,-,-TIA/EIA-644-A11 SCOPEThis Standard specifies the electrical characteristics of low voltage differential signalinginterface circuits, normally implemented in integrated circuit technology, that may beemployed when specified for the interchange of binary

28、 signals between:Data Terminal Equipment (DTE) and Data Circuit-Terminating Equipment (DCE),Data Terminal Equipment (DTE) and Data Terminal Equipment (DTE),or in any point-to-point, or multidrop interconnection of binary signals between equipment.The interface circuit includes a generator connected

29、by a balanced interconnecting mediato a load consisting of a termination impedance and a receiver(s). The interfaceconfiguration is a point-to-point or multidrop interface. The electrical characteristics of thecircuit are specified in terms of required voltage, and current values obtained from direc

30、tmeasurements of the generator and receiver (load) components at the interface points.The logic function of the generator and the receiver is not defined by this Standard, as it isapplication dependent. The generators and receivers may be inverting, non-inverting, ormay include other digital blocks

31、such as parallel-to-serial or serial-to-parallel converters toboost the data signaling rate on the interchange circuit as required by the application.Minimum performance requirements for the balanced interconnecting media are furnished.Guidance is given in Annex A, Section A.2 with respect to limita

32、tions on data signaling rateimposed by the parameters of the cable length, attenuation, and crosstalk for individualinstallations for a typical cable media interface.It is intended that this Standard will be referenced by other standards that specify thecomplete interface (i.e., connector, pin assig

33、nments, function) for applications where theelectrical characteristics of a low voltage differential signaling interface circuit is required.This Standard does not specify other characteristics of the DTE-DCE interface (such assignal quality, protocol, maximum data signaling rate, bus structure, and

34、/or timing)essential for proper operation across the interface.When this Standard is referenced by other standards or specifications, it should be notedthat certain options are available. The preparer of those standards and specificationsmust determine and specify those optional features which are r

35、equired for that application.Copyright Telecommunications Industry Association Provided by IHS under license with EIANot for ResaleNo reproduction or networking permitted without license from IHS-,-,-TIA/EIA-644-A22 DEFINITIONS, SYMBOLS AND ABBREVIATIONSFor the purposes of this Standard, the followi

36、ng definitions, symbols and abbreviationsapply:2.1 Data signaling rateData signaling rate - expressed in the units b/s (bits per second), is the significantparameter. It may be different from the equipments data transfer rate, which employs thesame units. Data signaling rate is defined as 1/tui wher

37、e tui is the minimum intervalbetween two significant instants.2.2 DTEData Terminal Equipment2.3 DCEData Circuit-Terminating Equipment2.4 LVDSLow Voltage Differential Signaling2.5 Star (*)Star (*) - represents the opposite input condition for a parameter. For example, the symbolQ represents the recei

38、ver output state for one input condition, while Q* represents theoutput state for the opposite input state.Copyright Telecommunications Industry Association Provided by IHS under license with EIANot for ResaleNo reproduction or networking permitted without license from IHS-,-,-TIA/EIA-644-A33 APPLIC

39、ABILITY3.1 General applicabilityThe provisions of this Standard may be applied to the circuits employed at the interfacebetween equipments where information being conveyed is in the form of binary signals.Typical points of applicability for this Standard are depicted in Figure 1.DTEDCEGR GRBBLegend:

40、DTE = Data Terminal Equipment DCE = Data Circuit-termination EquipmentG = Generator R = ReceiverB = Balanced interconnecting mediaFigure 1 - Application of LVDS interface circuitsThe LVDS interface is intended for use where any of the following conditions prevail:a. The data signaling rate is too gr

41、eat for effective unbalanced (single-ended)operation.b. The data signaling rate exceeds the capability of TIA/EIA-422, TIA/EIA-485, orTIA/EIA-612 balanced (differential) electrical interfaces.c. The balanced interconnecting media is exposed to extraneous noise sources thatmay cause an unwanted volta

42、ge up to 1 V measured differentially between thesignal conductor and circuit common at the load end of the cable with a 50 resistor substituted for the generator.d. It is necessary to minimize electromagnetic emissions and interference with othersignals.3.2 Data signaling rateThe LVDS interface circ

43、uit will normally be utilized on data and timing, or control circuits.Actual maximum data signaling rate is NOT defined by this Standard. The limit isCopyright Telecommunications Industry Association Provided by IHS under license with EIANot for ResaleNo reproduction or networking permitted without

44、license from IHS-,-,-TIA/EIA-644-A4determined by the generator transition time characteristics, the media characteristics, thedistance between the generator and the load, and the required signal quality.A theoretical maximum limit is calculated at 1.923 Gb/s, and is derived from a calculationof sign

45、al transition time at the load assuming a loss-less balanced interconnecting media.The recommended signal transition time (tr or tf) at the load should not exceed 0.5 of theunit interval to preserve signal quality. This Standard specifies that the transition time ofthe generator into a test load be

46、260 ps or slower. Therefore, with the fastest generatortransition time, and a loss-less balanced interconnecting media, and applying the 0.5restriction, yields a minimum unit interval of 520 ps or 1.923 Gb/s theoretical maximumdata signaling rate. Employing a parallel bus structure (4, 8, 16, 32, et

47、c. - bus width) caneasily extend the obtainable equivalent bit rate into the multi-Gb/s range.A recommended maximum data signaling rate is derived from a calculation of signaltransition time at the load. For example, if a cable media is selected, a maximum signalrise time degradation is assumed to b

48、e 500 ps, since cables are not loss-less (500 psrepresents a typical amount of rise time distortion on 5 meters of cable media). Therefore,allowing a 500 ps degradation of the signal in the interconnecting cable yields a 760 ps(fastest) signal at the load. Therefore, with the fastest generator trans

49、ition time, and acable with only 500 ps of signal degradation (transition time), and applying the 0.5restriction, yields a minimum unit interval of 1.520 ns or 655 Mb/s recommended maximumdata signaling rate based on this set of assumptions. Maximum data signaling rate is thusapplication dependent.Generators and receivers meeting this Standard need not operate to the theoreticalmaximum data