ARMY MIL-DTL-62737 A-1998 PRINTED WIRING ASSEMBLY COMPUTER《电脑印刷线路装配》.pdf

1、. MIL-DTL-62737A W 9999906 2059343 O99 W INCH-POUNDI MIL-DTL-6273 7A(AT) 23 Januarv 1998 SUPERSEDING 16 March 1992 MIL-P-6273 7(AT) DETAIL SPECIFICATION PRINTED WIRING ASSEMBLY, COMPUTER This specification is approved for use by U. S. Army Tank-automotive and Armaments Command, Department of the Arm

2、y, and is available for use by all Departments and Agencies of the Department of Defense. 1. SCOPE 1.1 Scope. This specification covers a Computer Printed WUing Assembly, referred to herein as the PWA. This is one of six printed Wiring assemblies that comprise the Simplified Test EquipmentInternal C

3、ombustion Engine-Reprogrammable (STEACE-R) Vehicle Test Meter (VTM) (see Drawing 12259265). 2. APPLICABLE DOCUMENTS 2.1 General. The documents listed in this section are specified in sections 3 and 4 of this specification. This section does not include documents in other sections of this specificati

4、on or recommended for additional information or as examples. While every effort has been made to ensure the completeness of this list, document users are cautioned that they must meet all specified requirement documents cited in sections 3 and 4 of this specification, whether or not they are listed.

5、 Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving this document should be addressed to: U. S. Army Tank-automotive and Armaments Command, ATTN: AMSTA-TR-EBLUE, Warren, MI 48397-5000, by ushg the Standardization Document Improvement P

6、roposal (DD Form 1426) appearing at the end of this document, or by letter. AMSC N/A FSC 5998 DISTRTBUTION STATEMENT A. Approved for public release; distribution is unlimited. Licensed by Information Handling ServicesMIL-DTL-b2737A = 9999906 2059344 T25 MIL-DTL-6273 7A(AT) 2.2 Government documents.

7、2.2.1 Specifications, standards. and handbooks. The following specifications, standards, and handbooks form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issue of the Department of Defense Index of Specificat

8、ions and Standards (DoDISS) and supplement thereto, cited in the solicitation (see 6.2). STANDARDS DEPARTMENT OF DEFENSE MIL-STD-8 1 O - Environmental Test Methods and Engineering Guidelines (see 4.2.1). (Unless otherwise indicated, copies of the above specifications, standards, and handbooks are av

9、ailable fkom the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19 1 1 1-5094.) 2.2.2 Other Government documents. drawings. and publications. The following other Government documents, drawings, and publications form a part of this document to the extent specif

10、ied herein. Unless otherwise specified, the issues are those cited in the solicitation. -. DRAWINGS DEPARTMENT OF DEFENSE 12259256 - Printed Wuing Assembly, Computer. (Copies of these drawings are available from the U.S. Army Tank-automotive and Armaments Cornmand, AMSTA-TR-EBLUE, Warren, MI 48397-5

11、000.) 2.3 Non-Government publications. The following documents form a part of this document to the extent specied herein. Unless otherwise specified, the issues of the documents which are DoD adopted are those listed in the issue of the DoDISS cited in the solicitation. Unless otherwise specified, t

12、he issues of documents not listed in the DoDISS are the issues of the documents cited in the solicitation (see 6.2). AMERICAN NATIONAL STANDARD INSTITUTE (ANSI) ANSI/IPC J-STD-O01 - Requirements for Soldered Electrical and Electronic Assemblies. 2 Licensed by Information Handling Services MIL-DTL-b2

13、737A 99999Ob 2059345 961 Source Pl-5,6 (Application for copies should be addressed to the American National Standard Institute, 11 West 42nd Street, New York, NY 10036.) Voltage Current +5 Vdc L/ 285 mA2/ 2.4 Order of precedence. In the event of a conflict between the text of this document and the r

14、eferences cited herein, the text of this document takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUkEMENTS 3.1 First article. When specified (see 6.2), a sample shali be subjected to first article in

15、spection in accordance with 4.1.1. 3.2 Desim materials. and manufacturing processes. Design, materials, and manufacturing process selection shall be as specified herein and in applicable referenced specifications, standards, and drawings. Materiais shall be uniform and free Com imperfections or defe

16、cts which affect their performance and serviceability. Ail metailic parts shail be made from corrosion resistant metals or treated with corrosion-resistant materials. Asbestos and Cadmium materials shali not be used in any form in any part of the PWA. No item, part or assembly shail contain radioact

17、ive materials in which the specific activity is greater than 0.002 microcuries per gram or activity per item equals or exceeds 0.01 microcuries. 3.2.1 Recycled. recovered. or environmentally meferable materiais. Recycled, recovered, or environmentally preferable materials should be used to the maxim

18、um extent possible provided that the material meets or exceeds the operational and maintenance requirements, and promotes economically advantageous life cycle costs. 3.3 Operating reauirements. Each PWA shall provide the following functional, operational, and performance capabilities. 3.3.1 Input po

19、wer. The PWA shall not require more than the current specified in table I. 3.3.2 Complimentary metal oxide semiconductor (CMOS) logic levels. Unless otherwise specified (see 6.2), CMOS logic levels accepted by and output from the PWA shaii be as follows: 3 Licensed by Information Handling Servicesi

20、MIL-DTL-bZ737A 9999906 205934b 8T8 Pin . Logic Level Input High (Logic Level 1) = 3.5 Vdc minimum (min.) Input Low (Logic Level O) = 1.5 Vdc maximum (max.) Output High (Logic Level 1) = 4.5 Vdc min. Output Low (Logic Level O) = 0.5 Vdc max. 3.3.3 Input isolation. (NOTE: A i“ following a capitalized

21、signal name denotes logic negation.) 3.3.3.1 EF1/ - EF41. INTERRUPT/. and CLEAR/ isolation. Logic levels applied to any one of the Pl-50, Pl-52, Pl-53, Pl-54, Pl-56, and Pl-62, shall have no effect on nor be affected by logic levels applied at any of the other pins specified in this paragraph. 3.3.3

22、.2 External input isolation. Logic levels applied to any one of Pl-76, Pl-77, Pl-79, P 1-8 1, P 1-69, P1-7 1, P 1-73, and P 1-75 shall have no effect on nor be affected by logic levels applied at any of the other pins specified in this paragraph. 3.3.4 Reset. 3.3.4.1 Power-up reset. Signals at pins

23、Pl-68, U1-3, U13-1, U13-13, U22-1, U24-4, U24-10, and U254 shall conform to the waveforms shown in figure 1 as +5.0 Vdc is applied to P1-5 and Pl-6. 3.3.4.2 CLEAR/. Applying a logic level O to Pl-62 shall bring P1-68. to logic level O in less than 62 nanoseconds (ns). 3.3.4.3 States durine; power-up

24、 reset or CLEAR/. While Pl-62 is held at logic level O, the following pins shail be,at the logic level designated in table II. TAB P 1-29 Pl-30 Pl-31 Pl-32 Pl-33 Pl-34 Pl-35 Pl-37 Pl-38 Pl-72 U1-4,17-20 U9-20 O O O O O O O O O 1 O 1 :AR/. - 4 Licensed by Information Handling Services MIL-DTL-62737A

25、m 9999906 2059347 734 m TABLE II. MIL-DTL-6273 7A(AT) qic levels durint Pin J11 Pins i-7, 9-11, 12 J12-1 513 Pins I, 5,9, 11, 12 514 Pins I, 7, 10 IT22 Pins l, 5, 7, 9, 10, 12 U23 Pins 13, 14, 15 U24 Pins 3,ll U25-3 U27-15 P1-46 P 1-64 P1-65 P 1-74 P1-78 u1-2 u2 Pins 1,26 u3 Pins 1,26 u4 Pins 1,26 u

26、5 Pins 1,26 U6 Pins 1, 26 u7 Pins 1,26 U13-6 U17-1 u21-1 U24 Pins 5,9 U25-5 U26 Pins 7,9, 10, 12-15 U27-13 Loeic Level O O O O O O O O 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 Licensed by Information Handling Services MIL-DTL-62737A 999990b 2059348 b70 MIL-DTL-6273 7A(AT) 3.3.4.4 Power-uddown memorv

27、protection. Whenever the voltage at P1 pins 5 and 6 goes below 4.5 V, U33-5 shall maintain a voltage of no more than 0.4 V until the voltage at P1 pins 5 and 6 is less than 3.0 V. The voltage at U33-5 shall track the voltage at P1 pins 5 and 6. Ifthe voltage at P1 pins 5 and 6 increases to a voltage

28、 greater than 4.6 V from a voltage less than 4.5 V, U33-5 shall maintain an output voltage of not greater than 0.4 V for a period of not less than 208 milliseconds (ms) and return to the voltage present at P1 pins 5 and 6 within 3 12 ms. 3.3.5 Clock frequencies. 3.3.5.1 Clock oscillator. The frequen

29、cy of the signal at Y1-8, U12-3, and U15-1 shall be 4.000 megahertz (MHz) f. 4.00 kilohertz (kHi). 3.3.5.2 2 MHZ clock. The frequency of the signal at Pl-83 and U12-2 shall be 2.000 MHz 2 400 Hz. 3.3.5.3 400 kHz clock. The frequency of the signal at Pl-67 and U14-2 shall be 400.0 k-Hz 5 400 Hz. 3.3.

30、5.4 200 kHz clock. The frequency of the signal at Pl-70 shall be 200.0 IrHz - + 200 Hz. 3.3.6 Microprocessor outputs and inputs. 3.3.6.1 Hi logic levels at pins 2 through 10,21 , and 23 through 25 must remain the same) when MWR/ (UZO-17) and a chip select fiom table IX conform to the waveforms in fi

31、gure 10. 3.3.9 ATE Test. The PWA shall pass TACOM approved ATE test installed in TACOM approved ATE or equivalent. 3.3.1 O soldering. Soldering shall meet or exceed the requirements of ANSz/IpC J-STD-001. 3.4 Interface reauirements. 3.4.1 Overall envelope. Overall envelope of the PWA sha be in accor

32、dance with drawing 12259256. 10 Licensed by Information Handling ServicesflIL-DTL-62737A m 999990b 2059353 T38 m MIL-DTL-6273 7A(AT) 3.5 Ownership and support requirements. The PWA shall meet the following logistics requirements. 3.5.1 Interchangeability. Interchangeability tolerances should permit

33、parts, subassemblies and assemblies to be used in their parent assemblies without regard to the source of supply or manufacturer. Parts, subassemblies and assemblies having the full range of dimensions and characteristics permitted by the specification governing the part, subassembly or assembly sho

34、uld be usable as replacement items without selection and without departure from the specified performance guidelines of the parent items. 3 S.2 Identification marking. Unless otherwise specified (see 6.2), identification marking shall be permanent and legible and shall include as a minimum the follo

35、wing: a. Nomenclature “PRINTED WIRING ASSEMBLY, COMPUTER”. b. Military part number. c. Manufacturers CAGE code and name. d. Manufacturers serial number. e. Contract number. f. Symbol “US”. 3.6 Ouerating environment requirements. The PWA shall operate under the following environmental condition, with

36、out degradation in performance: 3.6.1 Temperature. 3.6.1.1 High temperature (operating). The PWA shall be capable of operation without damage or malfunction at a high temperature of 125F (52C) (without solar radiation). 3.6.1.2 Low temperature (operating). The PWA shall be capable of operation witho

37、ut damage or malfunction at a low temperature of 20F (-7C). For ambient temperature below 20F (-7”C), the test set shall be operated in a shelter. 3.6.1.3 Hiah temperature (nonoperating). The PWA shall be capable of being stored and transported in its case without damage at an ambient temperature of

38、 plus 160F (71C). 3.6.1.4 Low temperature (nonoperating). The PWA shall be capable of being stored and transported in its case without damage in ambient temperatures of minus 60F (-51 OC). 3.6.2 Fungus. Au nonmetallic materiais not inherently fungistatic shall function in a fungus environment withou

39、t adversely affecting the operatiodperformance of PWA. 11 Licensed by Information Handling ServicesMIL-DTL-bZ737A m 999990b 2059354 974 m 3.6.3 Shock. The PWA shall evidence no degradation of fiuiction and meet the requirements of 3.3 when subjected to the shock test. 3.6.4 Vibration. The PWA shall

40、evidence no degradation of function and meet the requirements of 3.3 when subjected to the vibration test. 3.6.5 Burn-in. Unless otherwise specified (see 6.2), the PWA shali be subjected to and pass a “power on burn-in prior to the inspections listed in 4.1. 4. VERIFICATION 4.1 Classification of ins

41、pections. The inspection requirements specified herein are classified as follows: a. First article inspection (see 4.1. I). b. Conformance inspection (CI) (see 4.1.2). 4.1.1 First article inspection. Unless otherwise specified (see 6.2), the Government shaii select one PWA produced under the product

42、ion contract for first article inspection. First article sample shall include all the verifications of table X. 4.1.2 CI 100% insuection. CI shall be conducted on ali items (100% inspection) and shall include those examinations and tests from table X, as specified in the contract. TABLEX. Titie Desi

43、gn, materials, . To determine conformance to 3.3.7.9, a logic analyzer shall be used to vem that the rising edge of the signal at the active port clock, as specified by table V, occurs after the rising edge of OEN-Q/ when IOF/7 is at logic level 1. 4.2.3.7.10 Microprocessor clock fieauency select. T

44、o determine conformance to 3.3.7.10, a logic analyzer shall be used to veri that the signals at U13 pins 1, 3, 5, 6, 9, 11, and 12 conform to the waveforms of figure 4 when selected by the requirements Of 3.3.7.8 and clocked by the requirements of 3.3.7.9. 4.2.3.7.11 Memory bank select. To determine

45、 conformance to 3.3.7.11, a logic analyzer shall be used to ver that the level at U25-5 is equivalent to the logic level at U1-15 when selected by the requirements of paragraph 3.3.7.8 and clocked by the requirements of paragraph 3.3.7.9. 4.2.3.7.12 Bootstrap EPROM pane select. To determine conforma

46、nce to 3.3.7.12, a logic analyzer shall be used to ve that the logic levels at U24-5 and U24-9 are equivalent to the logic levels at U1-15 and U1-14 when selected by the requirements of 3.3.7.8 and clocked by the requirements of 3.3.7.9. 4.2.3.7.13 Memory chip select. To determine conformance to 3.3

47、.7.13, a logic analyzer shall be used to veriq that the memory chip select outputs conform to the requirements of tables Vi and VII. 4.2.3.8 Memory. 4.2.3.8.1 Bootstrap EPROM read. To determine conformance to 3.3.8.1, a logic analyzer shall be used to verify the logic levels on the data BUS (see 6.3

48、) when valid address and control signals are supplied to U9 as shown in the waveforms of figure 5. 4.2.3.8.2 SRAM write. To determine conformance to 3.3.8.2, U8 shall be written to by supplying the control signals and valid data as shown in the waveforms of figure 6. The method of 4.2.3.8.3 shall be

49、 used for verification. 17 Licensed by Information Handling Services MIL-DTL-b2737A m 9999906 2059360 178 m MIL-DTL-6273 7A(AT) 4.2.3.8.3 SRAM read. To detennine conformance to 3.3.8.3, a logic analyzer shail be used to vem that the logic levels on the data BUS conform to those written by the method of 4.2.3.8.2 when validaddress and control signals are supplied to U8 as shown in the waveforms of figure 7. 4.2.3.8.4 EEPROM byte write. To determine conformance to 3.3.8.4, each EEPROM (U2 through U7) shall be written to by supplying the contro