ATIS 0900105 09-2013 Synchronous Optical Network (SONET) C Network Timing and Synchronization.pdf

1、 AMERICAN NATIONAL STANDARD FOR TELECOMMUNICATIONS ATIS-0900105.09.2013 SYNCHRONOUS OPTICAL NETWORK (SONET) NETWORK ELEMENT TIMING AND SYNCHRONIZATION As a leading technology and solutions development organization, ATIS brings together the top global ICT companies to advance the industrys most-press

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11、 The initial fractional frequency offset magnitude shall be less than 0.05 ppm. Initial fractional frequency offset (in ppm) is defined here as: nkknkxnny001221006.0where: 0 is the sample period in seconds, n+1 is the number of phase samples in the measurement period, n0 = 60 seconds, xkare the phas

12、e samples in ns (xkis the sample 64 s after entry into holdover). Any frequency drift rate magnitude shall be less than 5.8 x 10-6 ppm/sec9. Frequency drift rate, D, is the time derivative of fractional frequency offset, defined here (in ppm/s) as: nkknknnkxnnnD02201161612306.0where: 0is the sample

13、period in seconds, n+1is the number of phase samples in the measurement period, n0 = 2000 seconds, 95.8 106ppm/s corresponds to a frequency drift of 0.5 ppm in a 24-hour period. ATIS-0900105.09.2013 7 xkare the phase samples in ns (xkis a sample taken at a time greater than or equal to 64 s after en

14、try into holdover). c) The fractional frequency offset at the output of the SONET NE, relative to the input at the moment of reference loss, shall not exceed a magnitude of 4.1 ppm due to temperature variations. This allowance is for temperature effects only, which do not normally occur rapidly. 6.3

15、 Holdover Recovery An upper bound on the rate of frequency change during recovery from holdover is necessary to avoid excessive amounts of jitter encoded onto SONET asynchronous payloads (DS1 and DS3). The rate of change of frequency, D, shall not exceed 2.9 ppm/s. D is defined as: nkknknnkxnnnD0220

16、1161612306.0where: 0is the sample period in seconds, n+1 is the number of phase samples in the measurement period, n0= 1.0 second, xkare the phase samples in ns (xkis a sample any time after recovery from holdover is initiated). 6.4 Pull-in Range In order to accommodate line timing from a SONET elem

17、ent with an SMC in holdover, a SONET NE with an SMC shall be able to lock to a timing reference signal which is 20 ppm offset from the nominal frequency. An SMC is not required to pull-in to a reference signal when its input reference is beyond the SMCs specified pull-in range. 6.5 Hold-in Range To

18、ensure that an OC-N timed SONET NE with an SMC will track and remain locked to a reference signal, the hold-in range of the SMC shall be at least 20 ppm relative to the nominal reference frequency. ATIS-0900105.09.2013 8 Figure 1 - SMC TDEV upper limit for DS1 synchronization reference signals ATIS-

19、0900105.09.2013 9 Figure 2 - MTIE upper limit for SMC entering holdover ATIS-0900105.09.2013 10 Annex A (informative) A DS1 Wander Accumulation through SONET Islands A.1 General The OC-N output wander specification in Figure 1 is tighter than the wander specification in ATIS-0900101 for OC-N signals

20、 used as synchronization references. It is expected that the wander specification in ATIS-0900101 will be reconsidered when ATIS-0900101 is reviewed. The tighter specification was driven by studies of wander accumulation on DS1 signals transported through SONET islands. A SONET island is a SONET net

21、work with asynchronous interfaces as shown in Figure A.1. As these SONET islands are interconnected, jitter and wander can accumulate as DS1 signals are mapped and de-mapped from SONET signals. Jitter accumulation studies are documented in ATIS-0900105.03. A wander budget was developed for DS1 signa

22、ls transported over SONET and is included in Annex H of ATIS-0900105.03. This wander budget allocated 10.1 microseconds of wander per day to SONET NE synchronization noise and random pointer adjustments. This budget was developed using ITU-T Recommendation G.822 for slip performance as a guideline.

23、At present, ITU-T Recommendation G.822 is the only known specification for slip performance. ITU-T Recommendation G.822 specifies in a national and local network that there should be less than an average of 2.3 slips in 24 hours (46% of 5 slips in 24 hours) at least 98.9% of the time. Existing netwo

24、rk elements may not be able to continually measure conformance to this specification. Simulations of DS1s transported over SONET islands showed that this specification could not be met over several islands with wander at the level specified in ATIS-0900101. The simulations showed the slip objective

25、could be met by improved wander performance and, optionally, fewer islands. With fewer islands, the wander performance does not have to be improved as much. It was decided to tighten the wander performance specification by lowering the TDEV mask to the level now reflected in Figure 1. It was also de

26、cided that not all networks of large number of SONET islands need to be accommodated. ITU-T Recommendation G.801 states that the hypothetical Reference Connection “.does not represent the rare worst case connection; although it does aim to encompass the vast majority of connections.“ Simulations wit

27、h the SONET clock model meeting Figure 1 specifications showed a DS1 transported over a network of 8 VT isIands would have 1 or fewer slips per day 94.6% of the time, and 2 or fewer slips per day 99.0% of the time. A.2 Simulation Model Assumptions The wander accumulation studies referred to above we

28、re performed with simulation tools that allowed arbitrary numbers of VT and/or STS islands, each with an arbitrary number of pointer processing nodes. Each node was synchronized by a clock phase noise model that contained a Flicker Phase Modulation (FPM) component and White Frequency Modulation (WFM

29、). The resulting phase noise was filtered by a single-pole, low-pass filter, which represented the SONET NE clock. The amplitudes of each of these components and the low-pass filter bandwidth were specified as input to the simulation. The model allowed, if desired, different phase noise component am

30、plitudes at each node, different numbers of nodes per island, and mixtures of VT and STS islands in the same network. VT pointer processors were assumed to have a 2-byte threshold spacing, and STS pointer processors were assumed to have a 4-byte threshold spacing. Finally, the desynchronizers in eac

31、h island were not modeled, as these do not affect long-term phase variation and DS1 slip performance. ATIS-0900105.09.2013 11 The WFM noise component was produced by generating a Gaussian white noise random sequence with zero mean and standard deviation equal to the specified amplitude, and then int

32、egrating this process. To avoid having to change the amplitude to keep TDEV the same every time the time step was changed, the samples were actually generated at fixed time intervals (chosen as 6.5 s here), and an equal portion of each sample was added at each time step. The FPM noise component was

33、produced by generating a Gaussian white noise random sequence with zero mean and standard deviation equal to the specified amplitude, and then passing this sequence through a set of filters as described in Efficient Numerical and Analog Modeling of Flicker Noise Processes and implemented in Large Si

34、mulation of Flicker Noise (see Annex D). The simulator used a single stream of white, Gaussian, random samples, with each filter receiving a now random sample when needed. This ensured that the noise at any node was statistically independent of the noise at any other node, to the extent that the ran

35、dom number generator produced statistically independent samples. The simulation results described at the end of the above subclause in this annex were for a network of 8 VT islands with 10 pointer processor nodes per island. The SONET NE clock low-pass filter bandwidths were set to 0.1 Hz, and the F

36、PM and WFM amplitudes at each node (of each island) were chosen such that TDEV for the resulting phase noise (prior to low-pass filtering) just met the mask of Figure 1. For each simulation case (i.e., for the 8-VT island case described above and for various other cases), 300 independent replication

37、s of a 1-day simulation were run. At the end of each run, the state of the random number generator was saved. This state was used to initialize the random number generator for the next run. At the beginning of each run, the pointer processor buffer fills were set randomly. This guaranteed that each

38、run produced phase variation results that were representative of the entire population of possible phase variations (for the given levels of clock phase noise) and were statistically independent of phase variation results produced on other runs (to the extent that the random number generator produce

39、d statistically independent samples). To obtain slip performance, it is necessary to account for all the wander components in the DS1 wander budget in Annex H of ATIS-0900105.03. However, it was not practical to run multiple, independent replications of 1-day simulations of DS1-to-DS3 mapping and of

40、 DS1-to-VT1.5 mapping (the computational requirements for this would have been prohibitive). In addition, a model for the component due to temperature effects on the fiber was not available. Therefore, these components were not simulated; they were accounted for with the approximate model described

41、below. The component of DS1 wander due to switch synchronization was simulated using a random phase noise model whose MTIE and TDEV just met DS1 Reference MTIE and TDEV masks shown in ATIS-0900101. This model is similar to the phase noise model in the SONET islands simulator (described above); the m

42、ain difference is that the noise levels for switch synchronization are somewhat higher. For each simulation case, 300 independent replications of each of two switch synchronization phase noise signals were simulated. The state of the random number generated was saved and used to initialize the next

43、run, as described above. For each replication of a simulation case, a SONET islands simulation was run, followed by two switch synchronization phase noise simulations. In this manner, all 900 runs were statistically independent of each other. The phase due to both random pointer adjustments/clock no

44、ise in SONET NEs and switch synchronization was obtained by adding together the phases obtained for each of the three waveforms for each replication. DS1 slip performance was obtained by using the above phase (due to both random pointer adjustments/clock noise and switch synchronization) as input to

45、 a slip buffer model. In this model, the slip buffer size is equal to the sum of the frame size and the hysteresis. The buffer fill at any given time is equal to the sum of the initial buffer fill, the DS1 phase input (from the SONET islands and switch synchronization simulations), and the total pha

46、se due to all slips up to that time. After computing the phase at each time step, it is checked whether either buffer edge is exceeded. If a buffer edge is exceeded, a slip equal to the frame size in the opposite direction (i.e., towards the other buffer edge) is generated. For each of the 300 indep

47、endent replications (for one case), the slip buffer simulation was run 51 times, with a different slip buffer initial condition for each run. The initial buffer fills were chosen to be 0., 0.02, 0.04, ., 1.0 of the total slip buffer size. This set of initial conditions assumes that the initial buffe

48、r fill at the beginning of a randomly-chosen, 24-hour period is uniformly distributed over the buffer size. For ATIS-0900105.09.2013 12 each simulation case, the total number of slip buffer simulations was (51)(300) = 15,300. For each of these runs, the number of slips was recorded; a statistical an

49、alysis was performed on the results of all the runs to obtain estimates of the probabilities of obtaining various numbers of slips in one day. To account for the fact that the wander components due to DS1-to-DS3 mapping, DS1-to-VT1.5 mapping, and temperature effects on the fiber were not simulated, the slip buffer frame size and hysteresis were reduced by the wander budget amounts for these components. The total wander budget for these three components is 4.2 s. Therefore, in t