1、raising standards worldwideNO COPYING WITHOUT BSI PERMISSION EXCEPT AS PERMITTED BY COPYRIGHT LAWBSI Standards PublicationPrinted boardsPart 14: Device embedded substrate Terminology / reliability / design guideDD IEC/PAS 62326-14:2010National forewordThis Draft for Development is the UK implementat
2、ion of IEC/PAS 62326-14:2010.The UK participation in its preparation was entrusted to Technical CommitteeEPL/501, Electronic assembly technology.A list of organizations represented on this committee can be obtained onrequest to its secretary.This publication does not purport to include all the neces
3、sary provisions of acontract. Users are responsible for its correct application. BSI 2010ISBN 978 0 580 69325 0ICS 31.180Compliance with a British Standard cannot confer immunity fromlegal obligations.This Draft for Development was published under the authority of theStandards Policy and Strategy Co
4、mmittee on 30 November 2010.Amendments issued since publicationDate Text affectedDRAFT FOR DEVELOPMENTDD IEC/PAS 62326-14:2010IEC/PAS 62326-14Edition 1.0 2010-09PUBLICLY AVAILABLE SPECIFICATIONPRE-STANDARD Printed boards Part 14: Device embedded substrate Terminology / reliability / design guide INT
5、ERNATIONAL ELECTROTECHNICAL COMMISSION XBICS 31.180 PRICE CODEISBN 978-2-88912-180-9 Registered trademark of the International Electrotechnical Commission colourinside 2 PAS 62326-14 IEC:2010(E) CONTENTS FOREWORD.6 1 Scope.8 2 Normative references .8 3 General definitions .9 3.1 Technology of the de
6、vice embedded substrate 9 3.2 Substrate 12 3.3 Jisso mounting and interconnection.13 3.4 Structure and terminology .15 3.4.1 General .15 3.4.2 Device embedding by conventional process.17 3.4.3 Electrical connection by vias after device embedding 19 3.4.4 Embedding of various devices over multiple la
7、yers 20 4 Test methods .22 4.1 General .22 4.2 Structure of TEG (Test Equipment Group Test vehicle) 22 4.3 Test circuit 24 4.4 Test specimen (TEG) and example of test substrate26 5 Test items and test equipment27 5.1 General .27 5.2 Test for resistance of conductor 28 5.3 Resistance to over current.
8、29 5.4 Withstand voltage30 5.5 Insulation resistance .30 5.6 Peeling strength of conductor32 5.7 Pull-off strength of plated through hole32 5.8 Adhesivity of plated film 32 5.9 Solderability 33 5.10 Thermal shock (vapour phase cold heat cycle) 34 5.11 Thermal shock (high temperature) .35 5.12 Flamma
9、bility36 5.13 Bow and twist36 5.14 Migration .37 6 Indication, packaging and storage 37 7 Design guide 38 7.1 General .38 7.2 Structure of device embedded substrate38 7.2.1 General .38 7.2.2 Specification of the front and back surfaces of a device embedded substrate .38 7.2.3 Definition of layers of
10、 a device embedded substrate 40 7.2.4 Definitions of insulation layer thickness, conductor spacing and distance between electrode and conductor spacing (hereafter called “electrode”) at a terminal 44 7.3 Conditions for base .47 7.4 Conditions for embedding devices .48 DD IEC/PAS 62326-14:2010PAS 623
11、26-14 IEC:2010(E) 3 7.5 Requirement for embedding devices51 7.6 Design specification of device embedded substrate.52 7.6.1 General .52 7.6.2 Items to be included in the design specification .52 Annex A (informative) Specimen for surface resistance measurement of electronic circuit board .57 Annex B
12、(informative) Insulation resistance measurement of inner layer of electronic circuit board .58 Annex C (informative) Specimen for interlayer insulation resistance measurement for multilayer circuit board 59 Annex D (informative) Electronic wiring board product system .60 Annex E (informative) Steps
13、of electronic circuit board assembly and main applications 61 Bibliography62 Figure 1 Examples of device embedded substrate .8 Figure 2 Completed device embedded substrate (pad connection).9 Figure 3 Completed device embedded substrate (via connection) 9 Figure 4 Structure of a device embedded subst
14、rate using a passive device embedded substrate as a base and then a active and/or a passive device is mounted and then covered by resin (Pad connection type)10 Figure 5 Structure of a device embedded substrate using a ceramic board as the base (via connection type) 10 Figure 6 Entire structure of de
15、vice embedded substrate.15 Figure 7 Base (typical structure) 15 Figure 8 Base (Cavity structure).15 Figure 9 Base (insulator)16 Figure 10 Base (conductive carrier metal plate) 16 Figure 11 Passive device embedded ceramic substrate used as a base.16 Figure 12 Ceramic board used as base16 Figure 13a W
16、ire bonding connection and embedding of active device bear chip.17 Figure 13b Soldering connection and embedding of active device17 Figure 13c Soldering connection of square type passive device .17 Figure 13d Conductive resin connection and embedding of active device.18 Figure 13e Conductive resin c
17、onnection and embedding of square type passive device.18 Figure 13f Soldering connection into through hole and embedding of passive device .18 Figure 13 Embedding of device by conventional methods 18 Figure 14a Connection by Cu plating after embedding of active device 19 Figure 14b Connection by Cu
18、plating after embedding of square type passive device 19 Figure 14c Conductive paste connection after embedding of active device package 19 Figure 14d Conductive paste connection after embedding of square type passive device chip .19 Figure 14 Via connection after embedding .19 Figure 15 Embedding o
19、f devices over multiple layers.20 Figure 16 Resin base substrate .20 DD IEC/PAS 62326-14:2010 4 PAS 62326-14 IEC:2010(E) Figure 17 Conductor and metal sheet/copper foil as the base substrate.21 Figure 18 Device embedded substrate using passive device embedded ceramic substrates as the base21 Figure
20、19 Device embedded substrate using passive device embedded ceramic substrates as the base second type .22 Figure 20 Schematic diagram of test circuit23 Figure 21 Multilayer wiring patterns 24 Figure 22 Conceptual structure of test circuit, comb-type capacitor, detection pattern of impedance, insulat
21、ion and migration .25 Figure 23 Example of TEG.26 Figure 24 Example of test circuit for connection evaluation 26 Figure 25 Example of test circuit for insulation evaluation 27 Figure 26 Resistance per unit length of conductor pattern in relation with conductor width.28 Figure 27 The relation of cond
22、uctor width, conductor thickness and temperature rise with current.29 Figure 28 Definition of front and back surfaces of a device embedded substrate39 Figure 29 Definition of front and back surfaces of a device embedded substrate substrate mounted on a mother board.39 Figure 30 Definition of layers
23、of a pad-connection substrate 40 Figure 31 Illustration of virtual layers .41 Figure 32 Layer names in the via interconnection (I) 41 Figure 33 Layer names in the via interconnection (II) .42 Figure 34 Layer names in via connection (III).42 Figure 35 Definitions of dielectric gap and layer gap in th
24、e pad connection method .44 Figure 36 Definitions of dielectric gap and layer gap in the via connection method.45 Figure 37 Additional illustration of dielectric gap 45 Figure 38 Additional illustration of layer gap 46 Figure 39 Additional drawing52 Figure 40 Forbidden wiring area 53 Figure A.1 Test
25、 pattern for surface insulation resistance measurement.57 Figure B.1 Test pattern for insulation resistance measurement of inner layers 58 Figure C.1 Test patterns for interlayer insulation resistance measurement.59 Figure D.1 Electronic wiring board product system.60 Table 1 Classification of devic
26、e embedding11 Table 1 Classification of device embedding（ continued） 12 Table 2 Embedded device structure and fabrication process 13 Table 3 Jisso mounting and interconnection of the device embedded substrate .14 Table 4 Conduction test .28 Table 5 Resistance to over current and its test method 29 T
27、able 6 Withstand voltage and test method30 Table 7 Test methods of insulation resistance31 Table 8 Peeling strength of conductor and test method32 Table 9 Pull-off strength of plated through hole and test method32 DD IEC/PAS 62326-14:2010PAS 62326-14 IEC:2010(E) 5 Table 10 Adhesivity of plated film
28、and test method.32 Table 11 Solderability and test method 33 Table 12 Characteristics and test method for thermal shock.34 Table 13 Specification and test method for thermal shock35 Table 14 Flammability specification and test method36 Table 15 Specification and test method for bow and twist 36 Tabl
29、e 16 Specification and test method for migration .37 Table 17 Layer names of device embedding substrate .43 Table 18 Requirements to device assembly to base substrate of device embedded boards 47 Table 19 Embedding requirement 48 Table 20 Mounting methods of semiconductor devices.49 Table 21 Mountin
30、g method of devices50 Table 22 Embedding device .51 Table 23 Specification of device embedded substrate 54 Table 23 Specification of device embedded substrate （ continued） .55 Table 23 Specification of device embedded substrate （ continued ） 56 Table E.1 Steps of electronic circuit board assembly an
31、d main applications.61 DD IEC/PAS 62326-14:2010 6 PAS 62326-14 IEC:2010(E) INTERNATIONAL ELECTROTECHNICAL COMMISSION _ PRINTED BOARDS Part 14: Device embedded substrate Terminology / reliability / design guide FOREWORD 1) The International Electrotechnical Commission (IEC) is a worldwide organizatio
32、n for standardization comprising all national electrotechnical committees (IEC National Committees). The object of IEC is to promote international co-operation on all questions concerning standardization in the electrical and electronic fields. To this end and in addition to other activities, IEC pu
33、blishes International Standards, Technical Specifications, Technical Reports, Publicly Available Specifications (PAS) and Guides (hereafter referred to as “IEC Publication(s)”). Their preparation is entrusted to technical committees; any IEC National Committee interested in the subject dealt with ma
34、y participate in this preparatory work. International, governmental and non-governmental organizations liaising with the IEC also participate in this preparation. IEC collaborates closely with the International Organization for Standardization (ISO) in accordance with conditions determined by agreem
35、ent between the two organizations. 2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international consensus of opinion on the relevant subjects since each technical committee has representation from all interested IEC National Committees. 3) IEC Pu
36、blications have the form of recommendations for international use and are accepted by IEC National Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC Publications is accurate, IEC cannot be held responsible for the way in which they are used o
37、r for any misinterpretation by any end user. 4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications transparently to the maximum extent possible in their national and regional publications. Any divergence between any IEC Publication and the corre
38、sponding national or regional publication shall be clearly indicated in the latter. 5) IEC itself does not provide any attestation of conformity. Independent certification bodies provide conformity assessment services and, in some areas, access to IEC marks of conformity. IEC is not responsible for
39、any services carried out by independent certification bodies. 6) All users should ensure that they have the latest edition of this publication. 7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and members of its technical committees and
40、 IEC National Committees for any personal injury, property damage or other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC Publications. 8) At
41、tention is drawn to the Normative references cited in this publication. Use of the referenced publications is indispensable for the correct application of this publication. 9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of patent rights.
42、 IEC shall not be held responsible for identifying any or all such patent rights. A PAS is a technical specification not fulfilling the requirements for a standard, but made available to the public. IEC-PAS 62326-14 was submitted by the JPCA (Japan Electronics Packaging and Circuits Association) and
43、 has been processed by IEC technical committee 91: Electronics assembly technology. It is based on JPCA-EB01 (2009) 2ndedition. It is published as a double-logo PAS and JPCA. The text of this PAS is based on the following document: This PAS was approved for publication by the P-members of the commit
44、tee concerned as indicated in the following document Draft PAS Report on voting 91/893/PAS 91/910/RVD Following publication of this PAS, which is a pre-standard publication, the technical committee or subcommittee concerned may transform it into an International Standard. DD IEC/PAS 62326-14:2010PAS
45、 62326-14 IEC:2010(E) 7 This PAS shall remain valid for an initial maximum period of 3 years starting from the publication date. The validity may be extended for a single period up to a maximum of 3 years, at the end of which it shall be published as another type of normative document, or shall be w
46、ithdrawn. A list of all the parts in the IEC 62326 series, under the general title Printed boards, can be found on the IEC website. IMPORTANT The colour inside logo on the cover page of this publication indicates that it contains colours which are considered to be useful for the correct understandin
47、g of its contents. Users should therefore print this document using a colour printer. DD IEC/PAS 62326-14:2010 8 PAS 62326-14 IEC:2010(E) PRINTED BOARDS Part 14: Device embedded substrate Terminology / reliability / design guide 1 Scope This PAS is applicable to device embedded substrates fabricated
48、 by embedding discrete active and passive electronic devices into an inner layer of a substrate with electric connections by vias, conductor plating, conductive paste, and printing. The device embedded substrate may be used as a substrate to mount SMDs to form electronic circuits, as conductor and i
49、nsulator layers may be formed after embedding electronic devices. The purpose of this PAS is to obtain common understanding in design, fabrication and use of device embedded substrates in the industry. This PAS describes the substrate embedding devices including but not limited to module, integrated passive device (IPD), microelectroc
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