1、 g49g50g3g38g50g51g60g44g49g42g3g58g44g55g43g50g56g55g3g37g54g44g3g51g40g53g48g44g54g54g44g50g49g3g40g59g38g40g51g55g3g36g54g3g51g40g53g48g44g55g55g40g39g3g37g60g3g38g50g51g60g53g44g42g43g55g3g47g36g58for integrated circuit (IMIC version 1.3)ICS 31.200Logic digital integrated circuits Specification
2、for I/O interface model DRAFT FOR DEVELOPMENTDD IEC/TS 62404:2007DD IEC/TS 62404:2007This Draft for Development was published under the authority of the Standards Policy and Strategy Committee on 30 March 2007 BSI 2007ISBN 978 0 580 50352 8an international Standard, to extend the life of the Technic
3、al Specification or to withdraw it. Comments should be sent to the Secretary of the responsible BSI Technical Committee at British Standards House, 389 Chiswick High Road, London W4 4AL.The UK participation in its preparation was entrusted to Technical Committee EPL/47, Semiconductors.A list of orga
4、nizations represented on EPL/47 can be obtained on request to its secretary.This publication does not purport to include all the necessary provisions of a contract. Users are responsible for its correct application. Amendments issued since publicationAmd. No. Date Commentsthat UK experience can be r
5、eported to the international organization responsible for its conversion to an international standard. A review of this publication will be initiated not later than 3 years after its publication by the international organization so that a decision can be taken on its status. Notification of the star
6、t of the review period will be made in an announcement in the appropriate issue of Update Standards.According to the replies received by the end of the review period, the responsible BSI Committee will decide whether to support the conversion into National forewordThis Draft for Development was publ
7、ished by BSI. It is the UK implementation of IEC/TS 62404:2007.This publication is not to be regarded as a British Standard.It is being issued in the Draft for Development series of publications and is of a provisional nature. It should be applied on this provisional basis, so that information and e
8、xperience of its practical application can be obtained.Comments arising from the use of this Draft for Development are requested so TECHNICAL SPECIFICATION IECTS 62404First edition2007-02Logic digital integrated circuits Specification for I/O interface model for integrated circuit (IMIC version 1.3)
9、 Reference number IEC/TS 62404:2007(E) DD IEC/TS 62404:2007CONTENTS FOREWORD.4 INTRODUCTION.6 1 Scope.7 2 Normative references .7 3 Terms and definitions .7 4 Outline .7 4.1 General .7 4.2 Covered range of model 8 4.3 Language for circuits.8 4.4 Device model 8 4.5 Structure of model.8 4.6 Simulation
10、 .8 4.7 Relation to IBIS .8 5 Model structure 9 6 Detailed model description .14 6.1 Description rules .14 6.2 IC model file16 6.3 Package model file 42 6.4 Module model file 49 7 Levels of models 56 Annex A (informative) Model delivery flow58 Annex B (informative) Example of model description59 Fig
11、ure 1 Outline of the model8 Figure 2 Hierarchy of three models 9 Figure 3 Data structure of an IMIC model file for IC .11 Figure 4 Data structure of an IMIC model file for package12 Figure 5 Data structure of an IMIC model file for module13 Figure 6 Pad assignment .20 Figure 7 Example of circuit des
12、cription.24 Figure 8 Input stimulus 25 Figure 9 Diode equivalent circuit29 Figure 10 Diode characteristics30 Figure 11 NMOS transistor equivalent circuit .31 Figure 12 PMOS transistor equivalent circuit31 Figure 13 Gate channel characteristics of MOS transistor 32 Figure 14 Characteristics of diode
13、in MOS transistor33 Figure 15 NPN transistor equivalent circuit 35 Figure 16 PNP transistor equivalent circuit 35 Figure 17 Static characteristics of bipolar transistor .35 Figure 18 NMOS characteristics on regular grid .39 DD IEC/TS 62404:2007 2 Figure 19 MOS transistor model with two-terminal mode
14、l .39 Figure 20 Relationship between inner terminals and equivalent circuits of package .46 Figure 21 Relationship between outer terminals and equivalent circuits of package .47 Figure 22 Example of module circuit 53 Figure 23 Example of signal source of module .55 Figure A.1 Delivery flow of model
15、files .58 Figure B.1 IC structure.59 Figure B.2 Equivalent circuit 59 Table 1 Elements of model structures 10 Table 2 Levels of models .57 Table 3 Required elements of model for each level 57 DD IEC/TS 62404:2007 3 INTERNATIONAL ELECTROTECHNICAL COMMISSION _ LOGIC DIGITAL INTEGRATED CIRCUITS SPECIFI
16、CATION FOR I/O INTERFACE MODEL FOR INTEGRATED CIRCUIT (IMIC version 1.3) FOREWORD 1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising all national electrotechnical committees (IEC National Committees). The object of IEC is to promote inte
17、rnational co-operation on all questions concerning standardization in the electrical and electronic fields. To this end and in addition to other activities, IEC publishes International Standards, Technical Specifications, Technical Reports, Publicly Available Specifications (PAS) and Guides (hereaft
18、er referred to as “IEC Publication(s)”). Their preparation is entrusted to technical committees; any IEC National Committee interested in the subject dealt with may participate in this preparatory work. International, governmental and non-governmental organizations liaising with the IEC also partici
19、pate in this preparation. IEC collaborates closely with the International Organization for Standardization (ISO) in accordance with conditions determined by agreement between the two organizations. 2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an i
20、nternational consensus of opinion on the relevant subjects since each technical committee has representation from all interested IEC National Committees. 3) IEC Publications have the form of recommendations for international use and are accepted by IEC National Committees in that sense. While all re
21、asonable efforts are made to ensure that the technical content of IEC Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any misinterpretation by any end user. 4) In order to promote international uniformity, IEC National Committees undertake to apply
22、IEC Publications transparently to the maximum extent possible in their national and regional publications. Any divergence between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in the latter. 5) IEC provides no marking procedure to indicate its
23、approval and cannot be rendered responsible for any equipment declared to be in conformity with an IEC Publication. 6) All users should ensure that they have the latest edition of this publication. 7) No liability shall attach to IEC or its directors, employees, servants or agents including individu
24、al experts and members of its technical committees and IEC National Committees for any personal injury, property damage or other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and expenses arising out of the publication, use of, or reliance upon, thi
25、s IEC Publication or any other IEC Publications. 8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is indispensable for the correct application of this publication. 9) Attention is drawn to the possibility that some of the elements of thi
26、s IEC Publication may be the subject of patent rights. IEC shall not be held responsible for identifying any or all such patent rights. The main task of IEC technical committees is to prepare International Standards. In exceptional circumstances, a technical committee may propose the publication of
27、a technical specification when the required support cannot be obtained for the publication of an International Standard, despite repeated efforts, or the subject is still under technical development or where, for any other reason, there is the future but no immediate possibility of an agreement on a
28、n International Standard. Technical specifications are subject to review within three years of publication to decide whether they can be transformed into International Standards. IEC 62404, which is a technical specification, has been prepared by subcommittee 47A: Integrated circuits, of IEC technic
29、al committee 47: Semiconductor devices. DD IEC/TS 62404:2007 4 The text of this technical specification is based on the following documents: Enquiry draft Report on voting 47A/746/DTS 47A/751/RVCFull information on the voting for the approval of this technical specification can be found in the repor
30、t on voting indicated in the above table. This publication has been drafted in accordance with the ISO/IEC Directives, Part 2. A bilingual version of this publication may be issued at a later date. The committee has decided that the contents of this publication will remain unchanged until the mainte
31、nance result date indicated on the IEC web site under “http:/webstore.iec.ch“ in the data related to the specific publication. At this date, the publication will be transformed into an International standard, reconfirmed, withdrawn, replaced by a revised edition, or amended. DD IEC/TS 62404:2007 5 I
32、NTRODUCTION With an increase in speed of electronic systems, it becomes necessary to accurately predict electrical performance including noise in electronic systems with integrated circuits. Simulators have been used for this purpose. Simulators need accurate models for describing electrical propert
33、ies of integrated circuits. Semiconductor manufacturers and/or suppliers are required by their users to prepare device models for various simulation tools, some of which are not compatible with SPICE. In addition, since SPICE models contain proprietary process parameters, a non-disclosure agreement
34、is typically required to obtain these from the vendor. IBIS (I/O Buffer Interface Specification) has been proposed as a model for integrated circuits, which, approved as IEC 62014-1, has the following features: since electrical properties of I/O buffers are described in table format, disclosure of p
35、roprietary information such as process parameters is drastically reduced; it is easy to get IBIS models that are supported by many simulation tools; a public domain tool can convert SPICE models into IBIS models. However, IBIS models seem to have the following problems: the modeling of power and gro
36、und currents is insufficient for accurate power and ground bounce analysis; since an IBIS model has only the final stage at output and input, it is difficult to model the effect of loading on circuit boards on output and input waveforms. The fixed model taken by IBIS has little flexibility for descr
37、ibing other circuitry; in order to simulate EMI with accuracy, more information such as material constant and three-dimensional structures is needed. DD IEC/TS 62404:2007 6 LOGIC DIGITAL INTEGRATED CIRCUITS SPECIFICATION FOR I/O INTERFACE MODEL FOR INTEGRATED CIRCUIT (IMIC version 1.3) 1 Scope The f
38、ollowing items are considered to standardize the electrical modeling of input signals, output signals, power supply and ground terminals of integrated circuits, in order to provide for analysis of electrical characteristics of equipment. 1) To standardize in order to solve current problems and in or
39、der to extend capabilities of analysis, on the basis of results of the past standardization activities. 2) To define more flexible description rules for electric circuits in order to provide more accurate analysis of printed circuit board. 3) To introduce the concept of modeling levels to exchange r
40、elevant data for each application. 4) To enhance electrical modeling for packages and modules. 2 Normative references The following referenced documents are indispensable for the application of this document. For dated references, only the edition cited applies. For undated references, the latest ed
41、ition of the referenced document (including any amendments) applies. IEC 62014-1:2001, Electronic design automation libraries Part 1: Input/output buffer information specifications (IBIS version 3.2) 3 Terms and definitions Under consideration 4 Outline 4.1 General The outline of this model is shown
42、 in Figure 1. DD IEC/TS 62404:2007 7 Characterized by table format Chip Package Buffer Input Signal Signal Pin (Output) Power Pin Signal Pin (Output) Buffer Buffer Signal Pin (Input) Ground Pin Signal Pin (Input) Characterized by table format Power Pin Ground Pin Input Signal Buffer IEC 180/07 Figur
43、e 1 Outline of the model 4.2 Covered range of model The model is described as circuits covering the whole or a part of the I/0 buffers and the package. 4.3 Language for circuits The circuits shall be described in extended SPICE format. The structure allows describing simple buffers, complex buffers,
44、 power and ground lines, packages and complex memory module boards in a unified format. 4.4 Device model The characteristics of non-linear devices redescribed in one-dimensional, two-dimensional or three-dimensional table format. 4.5 Structure of model The data of the model consists of integrated ci
45、rcuit, package and module portions. Therefore each portion can be generated independently. 4.6 Simulation The netlist of printed circuit board and the I/O buffer model defined by this specification provides accurate circuit simulation results. 4.7 Relation to IBIS Tools that can extract IBIS data fr
46、om this model are possible to develop. DD IEC/TS 62404:2007 8 5 Model structure The model shall describe the inside of ICs, packages and module boards as shown in Figure 2. The models of IC, package and module board consist of the elements given in Table 1. The data structures of IC, package and mod
47、ule board models are shown in Figure 3, Figure 4, and Figure 5, respectively. Package model IC model Module model Module Module IEC 181/07 Figure 2 Hierarchy of three models DD IEC/TS 62404:2007 9 Table 1 Elements of model structures File Element Description Header IC type, model version, model leve
48、l. External terminals IC external terminals (package pins). Pad assignment Connection between IC pads and package inner terminals. Circuit description Internal circuits and their connections. Input stimulus assignment Internal circuits and their stimuli to generate output waveforms. Input stimulus I
49、nput waveforms. Device model Characteristics of non-linear circuits in one-dimensional, two-dimensional and three-dimensional table data. Non-linear devices are transistors, diodes and so on. IC model file Package model reference Name of the package model to be used. Header Package name, model version, model level. Model name List of models in package circuit model. Inner terminal Cross-reference between internal terminals an
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