BS EN 165000-5-1998 Film and hybrid integrated circuits - Procedure for qualification approval《薄膜集成电路和混合集成电路 合格鉴定批准程序》.pdf

1、BRITISH STANDARD BS EN 165000-5:1998 Harmonized system of quality assessment for electronic components Film and hybrid integrated circuits Part 5: Procedure for qualification approval The European Standard EN 165000-5:1997 has the status of a British Standard ICS 31.200BSEN165000-5:1998 This British

2、 Standard, having been prepared under the direction of the Electrotechnical Sector Board, was published under the authority of the Standards Board and comes into effect on 15 March 1998 BSI 04-1999 ISBN 0 580 28890 0 National foreword This British Standard is the English language version of EN165000

3、5:1997 published by the European Electronic Components Committee (CECC) of the European Committee for Electrotechnical Standardization (CENELEC). The UK participation in its preparation was entrusted by Technical Committee EPL/47, Semiconductor devices, to Subcommittee EPL/47/1, Film and hybrid int

4、egrated circuits, which has the responsibility to: aid enquirers to understand the text; present to the responsible international/European committee any enquiries on the interpretation, or proposals for change, and keep the UK interests informed; monitor related international and European developmen

5、ts and promulgate them in the UK. A list of organizations represented on this subcommittee can be obtained on request to its secretary. Cross-references The British Standards which implement international or European publications referred to in this document may be found in the BSI Standards Catalog

6、ue under the section entitled “International Standards Correspondence Index”, or by using the “Find” facility of the BSI Standards Electronic Catalogue. A British Standard does not purport to include all the necessary provisions of a contract. Users of British Standards are responsible for their cor

7、rect application. Compliance with a British Standard does not of itself confer immunity from legal obligations. Summary of pages This document comprises a front cover, an inside front cover, pages i and ii, theEN title page, pages2 to21 and a back cover. This standard has been updated (see copyright

8、 date) and may have had amendments incorporated. This will be indicated in the amendment table on the inside front cover. Amendments issued since publication Amd. No. Date CommentsBSEN165000-5:1998 BSI 04-1999 i Contents Page National foreword Inside front cover Foreword 2 Text of EN 165000-5 3ii bl

9、ankEUROPEAN STANDARD NORME EUROPENNE EUROPISCHE NORM EN 165000-5 December 1997 ICS 31.200 Descriptors: Hybrid integrated circuits, qualification approval English version Film and hybrid integrated circuits Part 5: Procedure for qualification approval Integrierte Hybrid- und Schichtschaltungen Teil 5

10、 Verfahren fr die Bauartanerkennung This European Standard was approved by CENELEC on1997-10-01. CENELEC members are bound to comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration. U

11、p-to-date lists and bibliographical references concerning such national standards may be obtained on application to the Central Secretariat or to any CENELEC member. This European Standard exists in three official versions (English, French, German). A version in any other language made by translatio

12、n under the responsibility of a CENELEC member into its own language and notified to the Central Secretariat has the same status as the official versions. CENELEC members are the national electrotechnical committees of Austria, Belgium, Czech Republic, Denmark, Finland, France, Germany, Greece, Icel

13、and, Ireland, Italy, Luxembourg, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland and United Kingdom. CENELEC European Committee for Electrotechnical Standardization Comit Europen de Normalisation Electrotechnique Europisches Komitee fr Elektrotechnische Normung Central Secretariat: rue de

14、Stassart 35, B-1050 Brussels 1997 CENELEC All rights of exploitation in any form and by any means reserved worldwide for CENELEC members. Ref. No. EN165000-5:1997 EEN165000-5:1997 2 BSI 04-1999 Foreword This European Standard was prepared by the Technical Committee CENELEC/TC CECC/SC47AX, Film and h

15、ybrid integrated circuits. The text of the draft was submitted to the Unique Acceptance Procedure and was approved by CENELEC as EN165000-5 on1997-10-01. The following dates were fixed: This standard is intended to be read in conjunction with other parts of EN165000 which are: Part1: Generic specifi

16、cation Capability approval procedure; Part2: Internal visual inspection and special tests; Part4: Customer information, product assessment level schedules and blank detail specification. Part4 is considered an essential document for all users; in particular it includes a helpful introductory section

17、 which is aimed at potential customers and seeks to explain the underlying philosophy upon which the whole standard is based. Contents Page Foreword 2 1 Scope 3 2 Related documents 3 3 Qualification procedures 3 3.1 General 3 3.2 Marking 3 3.3 Validity of release for delivery 3 3.4 Application for Q

18、ualification Approval 3 3.5 Structural similarity 3 3.6 Materials, piece-parts and added components 3 3.7 Initial Qualification Approval 3 3.8 Granting of Qualification Approval 4 3.9 Maintenance of Qualification Approval 4 3.10 Procedure in the event of a failure in a periodic test 4 3.11 Withdrawa

19、l of Qualification Approval 4 4 Qualification Product Assessment Level Schedules 4 Q Product assessment level schedules 1 11 5-19 5 Blank detail specification 19 Table 1 9 20 latest date by which the EN has to be implemented at national level by publication of an identical national standard or by en

20、dorsement (dop) 1998-09-01 latest date by which the national standards conflicting with the EN have to be withdrawn (dow) 1998-09-01EN165000-5:1997 BSI 04-1999 3 1 Scope This specification applies to film and hybrid integrated circuits manufactured as catalogue products or as custom built products u

21、sing thick/thin film techniques and whose quality is assessed on the basis of Qualification Approval. Test methods are selected from EN165000-1. A Blank Detail Specification (BDS) is included to assist manufacturers and users in the preparation of detail specifications. Related documents, preferred

22、ratings and characteristics, and terminology are given in EN165000-1. 2 Related documents Normative references are listed in EN165000-1, to which should be added: 3 Qualification approval procedures 3.1 General The procedures in RP14 part II shall apply. 2.1 of EN165000-1 applies with the exceptions

23、 given in3.2 to 3.11. 3.2 Marking 1.5 of EN 165000-1 applies. 3.3 Validity of release for delivery Circuits may be released under Qualification Approval subject to the following conditions: a) the circuits conform with the requirements of the detail specification. b) the circuits, their added compon

24、ents, piece parts and materials are traceable to original manufacturers lot numbers. 3.4 Application for Qualification Approval Application shall be made to the ONH in accordance with 1.3 of RP14 part II. In addition, the manufacturer shall: a) conform with the eligibility requirements of2.1.1 of EN

25、165000-1. b) conform with the relevant detail specification based on the Blank Detail Specification (see clause 5) and the Qualification Product Assessment Level Schedules (Q-PALS) (see clause 4) contained in this document. 3.5 Structural similarity For the purposes of assessment testing, structural

26、 similarity can be used if the testing of one representative type of circuit gives at least the same quality level for the rest of the types which are grouped together. The CECC System Manager shall declare to the satisfaction of the ONS the method of operating the structural similarity plan within

27、the manufacturing facilities and agree the representative type(s) from each structurally similar group. For the Qualification Approval procedure two or more circuits can be considered structurally similar, and thus the required numbers of specimens for a test shall be selected from the combined prod

28、uction, when they have the same function type, use the same design rules, materials, processes and methods (for example a range of T-cell thick film attenuators using the same line of inks; or thin film D/A convertors using the same film material and same added components from the same supplier). On

29、ly those tests not specifically excluded in the Q-PALS may be considered for structural similarity. 3.6 Materials, piece-parts and added components 2.1.4 of EN165000-1 applies. 3.7 Initial Qualification Approval The schedules to be used for Qualification Approval testing on the basis of lot-by-lot a

30、nd periodic testing are given in the Q-PALS tables contained in this document. The procedure for initial Qualification Approval is given below. CECC00114 part II (RP14 part II) qualification approval of electronic componentsEN165000-5:1997 4 BSI 04-1999 The relevant Q-PALS for initial Qualification

31、Approval, release of products (lot-by-lot tests) and maintenance of Qualification Approval (periodic tests) collectively prescribe the minimum test programme on completed circuits. 1) Sampling The sample shall be representative of the range of circuits for which approval is sought. (See2.2.4 3) of E

32、N165000-1). The size of the sample and the criterion of acceptability depend on the relevant Q-PALS which it is intended to release against. 2) Tests The complete series of tests specified in the relevant Q-PALS contained in this document is required for the approval of circuits covered by one detai

33、l specification. The tests shall be carried out in the order given. Test and measurement procedures are given in clause 3 of EN165000-1. Samples used for group B, C b) there has been no break exceeding two years in the manufacturers declared periodic test schedule. 3.9.2 Changes to Qualification App

34、roval The manufacturer is required to notify the ONS of changes to his Qualification Approval in accordance with 1.9 of RP14 part II and 2.3.2 a) to h) of EN165000-1, where applicable. NOTEAll re-verification programmes are to be agreed with the ONS. 3.10 Procedure in the event of a failure in a per

35、iodic test The procedure described in 1.8 of RP14 part II shall apply. 3.11 Withdrawal of Qualification Approval The procedures in 1.10 and 1.11 of RP14 part II shall apply. 4 Qualification-product assessment level schedules NOTEThe following eleven Q-PALS are based upon corresponding PALS in EN1650

36、00-4. Q-PALS4,5,8,9,10 and11 are structured to include subgroups C1 and C2 so that the schedules correspond to CECC63000 Assessment Level KEN165000-5:1997 BSI 04-1999 5 The remaining Q-PALS corespond to CECC63000 Assessment Levels L and M. Q-PRODUCT ASSESSMENT LEVEL SCHEDULE1. Applicability. This as

37、sessment schedule is intended for use with solder assembled and/or bare die, non-hermetic encapsulated, unencapsulated, cavity or non-cavity devices, which are for use in benign mechanical and temperature environments. Subgroup A Tests: Device Screening100 % EN165000-1 Reference 1. Electrical test T

38、 amb . Those tests in the Detail Specification which define circuit functionality. 3.4 Subgroup B Tests (lot-by-lot): Device Sample Testing. IL S4 AQL0,4 % 1. Electrical test T amb(other than those specified for Screening). 3.4 2. External visual inspections. 3.3.2 Subgroup C Tests (6 monthly period

39、): Design Evaluation. Minimum sample8. Accept on0 failures. 1. Electrical test. All specified parameters T min& T max . a 3.4 2. Dimensions. 3.3.3 Subgroup D Tests (12 monthly period): Design Evaluation. Minimum sample3. Accept on0 failures. 1. Resistance of circuits to solder heat. (D) 3.5.11 2. So

40、lderability. (ND/D) 3.5.10 3. Robustness of terminations. (D) 3.5.12 4. Flammability. (D) 3.5.16 5. Resistance to solvents. (ND) 3.5.15 a Structural similarity rules do not apply. Process and Packaging requirements. 1. Substrate fabrication = class100000. 2. Substrate assembly (bare die) = class1000

41、00. 3. E.S.D precautions (where applicable) to CECC00015. 4. Pre-cap visual IL S4 AQL0,4 % minimum. 3.3.1EN165000-5:1997 6 BSI 04-1999 Q-PRODUCT ASSESSMENT LEVEL SCHEDULE2. Applicability. This assessment schedule is intended for use with solder assembled and/or bare die, non-hermetic encapsulated, u

42、nencapsulated, cavity or non-cavity devices, which are for use in benign mechanical and temperature environments. Subgroup A Tests: Device Screening100 % EN165000-1 Reference 1. Electrical test T amb . Those tests in the Detail Specification. which define circuit functionality. 3.4 Subgroup B Tests

43、lot-by-lot): Device Sample Testing. IL S4 AQL0,4 % 1. Electrical test T amb(other than those specified for Screening). 3.4 2. External visual inspection. 3.3.2 Subgroup C Tests (6 monthly period): Design Evaluation. Minimum sample8. Accept on0 failures. 1. Electrical Endurance1000h. Release after16

44、0h. a 3.5.14 2. Electrical test. All specified parameters T min& T max . a 3.4 3. Dimensions. 3.3.3 Subgroup D Tests (12 monthly period): Design Evaluation. Minimum sample3. Accept on0 failures. 1. Resistance of circuits to solder heat. (D) 3.5.11 2. Solderability. (ND/D) 3.5.10 3. Robustness of ter

45、minations. (D) 3.5.12 4. Flammability. (D) 3.5.16 5. Resistance to solvents. (ND) 3.5.15 a Structural similarity rules do not apply. Process and Packaging requirements. 1. Substrate fabrication = class100000. 2. Substrate assembly (bare die) = class100000. 3. E.S.D precautions (where applicable) to

46、CECC00015. 4. Pre-cap visual IL S4 AQL0,4 % minimum. 3.3.1EN165000-5:1997 BSI 04-1999 7 Q-PRODUCT ASSESSMENT LEVEL SCHEDULE3. Applicability. This assessment schedule is intended for use with solder assembled, and/or bare die, non-hermetic encapsulated, unencapsulated, cavity or non-cavity devices. T

47、hese hybrids are for use in benign mechanical environments but with demonstration of extreme temperature and humidity operation. Subgroup A Tests: Device Screening100 % EN165000-1 Reference 1. Change of temperature.10 cycles. 3.5.8 1) 2. Electrical test T amb . Those tests in the Detail Specificatio

48、n. which define circuit functionality. 3.4 Subgroup B Tests (lot-by-lot): Device Sample Testing. IL S4 AQL0,4 % 1. Electrical test T amb(other than those specified for Screening). 3.4 2. Electrical tests T min& T max . Those tests in the Detail Specification. which define circuit functionality. 3.4

49、3. External visual inspection. 3.3.2 Subgroup C Tests (6 monthly): Design Evaluation. Minimum sample8. Accept on0 failures. 1. Electrical Endurance1000 h. Release after160 h. a 3.5.14 2. Dimensions. 3.3.3 3. Damp heat cyclic or steady state. 3.5.4, 3.5.3 4. Change of temperature. a 3.5.8 2) Subgroup D Tests (12 monthly period): Design Evaluation. Minimum sample3. Accept on0 failures. 1. Resistance of circuits to solder heat. (D) 3.5.11 2. Solderability. (ND/D) 3.5.10 3. Robustness of terminations. (D) 3.5.12