BS EN 60191-6-5-2001 Mechanical standardization of semiconductor devices - General rules for the preparation of outline drawings of surface mounted semiconductor device packages - ).pdf

1、BRITISH STANDARD BS EN 60191-6-5:2001 IEC 60191-6-5:2001 Mechanical standardization of semiconductor devices Part 6-5: General rules for the preparation of outline drawings of surface mounted semiconductor device packages Design guide for fine-pitch ball grid array (FBGA) The European Standard EN 60

2、191-6-5:2001 has the status of a British Standard ICS 31.080.01 NO COPYING WITHOUT BSI PERMISSION EXCEPT AS PERMITTED BY COPYRIGHT LAWBS EN 60191-6-5:2001 This British Standard, having been prepared under the direction of the Electrotechnical Sector Policy and Strategy Committee, was published under

3、 the authority of the Standards Policy and Strategy Committee on 15 November 2001 BSI 15 November 2001 ISBN 0 580 38665 1 National foreword This British Standard is the official English language version of EN 60191-6-5:2001. It is identical with IEC 60191-6-5:2001. The UK participation in its prepar

4、ation was entrusted by Technical Committee EPL/47, Semiconductors, to Subcommittee EPL/47/4, Mechanical standardization, which has the responsibility to: A list of organizations represented on this Subcommittee can be obtained on request to its secretary. From 1 January 1997, all IEC publications ha

5、ve the number 60000 added to the old number. For instance, IEC 27-1 has been renumbered as IEC 60027-1. For a period of time during the change over from one numbering system to the other, publications may contain identifiers from both systems. Cross-references The British Standards which implement i

6、nternational or European publications referred to in this document may be found in the BSI Standards Catalogue under the section entitled “International Standards Correspondence Index”, or by using the “Find” facility of the BSI Standards Electronic Catalogue. A British Standard does not purport to

7、include all the necessary provisions of a contract. Users of British Standards are responsible for their correct application. Compliance with a British Standard does not of itself confer immunity from legal obligations. aid enquirers to understand the text; present to the responsible European commit

8、tee any enquiries on the interpretation, or proposals for change, and keep the UK interests informed; monitor related international and European developments and promulgate them in the UK. Summary of pages This document comprises a front cover, an inside front cover, the EN title page, pages 2 to 10

9、, an inside back cover and a back cover. The BSI copyright date displayed in this document indicates when the document was last issued. Amendments issued since publication Amd. No. Date CommentsEUROPEAN STANDARD EN 60191-6-5 NORME EUROPENNE EUROPISCHE NORM October 2001 CENELEC European Committee for

10、 Electrotechnical Standardization Comit Europen de Normalisation Electrotechnique Europisches Komitee fr Elektrotechnische Normung Central Secretariat: rue de Stassart 35, B - 1050 Brussels 2001 CENELEC - All rights of exploitation in any form and by any means reserved worldwide for CENELEC members.

11、 Ref. No. EN 60191-6-5:2001 E ICS 31.080.01 English version Mechanical standardization of semiconductor devices Part 6-5: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for fine-pitch ball grid array (FBGA) (IEC 60191-6-5:2001) N

12、ormalisation mcanique des dispositifs semiconducteurs Partie 6-5: Rgles gnrales pour la prparation des dessins dencombrement des dispositifs semiconducteurs montage en surface - Guide de conception pour les botiers matriciels billes et pas fins (FBGA) (CEI 60191-6-5:2001) Mechanische Normung von Hal

13、bleiterbauelemente Teil 6-5: Allgemeine Regeln fr die Erstellung von Gehusezeichnungen von SMD-Halbleitergehusen - Konstruktionsleitfaden fr Feinraster- Ball-Grid-Arrays (FBGA) (IEC 60191-6-5:2001) This European Standard was approved by CENELEC on 2001-10-01. CENELEC members are bound to comply with

14、 the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration. Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the Central Secretaria

15、t or to any CENELEC member. This European Standard exists in three official versions (English, French, German). A version in any other language made by translation under the responsibility of a CENELEC member into its own language and notified to the Central Secretariat has the same status as the of

16、ficial versions. CENELEC members are the national electrotechnical committees of Austria, Belgium, Czech Republic, Denmark, Finland, France, Germany, Greece, Iceland, Ireland, Italy, Luxembourg, Malta, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland and United Kingdom.NE 061-19-6:52001 - 2

17、 - Foreword The text of document 47D/437/FDIS, future edition 1 of IEC 60191-6-5, prepared by SC 47D, Mechanical standardization of semiconductor devices, of IEC TC 47, Semiconductor devices, was submitted to the IEC-CENELEC parallel vote and was approved by CENELEC as EN 60191-6-5 on 2001-10-01. Th

18、e following dates were fixed: latest date by which the EN has to be implemented at national level by publication of an identical national standard or by endorsement (dop) 2002-07-01 latest date by which the national standards conflicting with the EN have to be withdrawn (dow) 2004-10-01 Annexes desi

19、gnated “normative“ are part of the body of the standard. In this standard, annex ZA is normative. Annex ZA has been added by CENELEC. _ Endorsement notice The text of the International Standard IEC 60191-6-5:2001 was approved by CENELEC as a European Standard without any modification. _ Page2 EN6019

20、165:2001 BSI15November2001 2 601-19-6 5 IE:C0201(E) MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES Part 6-5: General rules for the preparation of outline drawings of surface mounted semiconductor device packages Design guide for fine-pitch ball grid array (FBGA) 1 Scope This part of IEC 60191 p

21、rovides common outline drawings and dimensions for all types of structures and composed materials of fine-pitch ball grid array (hereinafter called FBGA), whose terminal pitch is less than, or equal to, 0,80 mm and whose package body outline is square. The demand for area array style packages exists

22、 according to the multi-functioning and high performance of electrical equipment. The object of this design guide is to standardize outlines and secure interchangeability of FBGA packages. The terminal pitch and package outlines of these fine-pitch array packages are smaller than those of BGA packag

23、es. 2 Normative references The following normative documents contain provisions which, through reference in this text, constitute provisions of this part of IEC 60191. For dated references, subsequent amendments to, or revisions of, any of these publications do not apply. However, parties to agreeme

24、nts based on this part of IEC 60191 are encouraged to investigate the possibility of applying the most recent editions of the normative documents indicated below. For undated references, the latest edition of the normative document referred to applies. Members of IEC and ISO maintain registers of cu

25、rrently valid International Standards. IEC 60191-6:1990, Mechanical standardization of semiconductor devices Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages 3 Definitions For the purposes of this part of IEC 60191, the definitions contai

26、ned in IEC 60191-6 as well as the following definitions apply. 3.1 flanged type type whose package body size (body length and width) consists of its own flange which is composed around the encapsulation or lid 3.2 type of real chip size type whose package body size (body length and width) consists o

27、f an encapsulation just around the real chip only Page3 EN6019165:2001 BSI15November2001061-19-6 5 IE:C0201(E) 3 3.3 fine-pitch ball grid array (FBGA) packages with metal balls whose terminal pitch is less than, or equal to, 0,80 mm positioned in an array on the base plane of the package as external

28、 terminals. This package structure makes it possible to surface-mount the packages to the printed circuit board 3.4 material designation FBGA packages are classified according to the following two material designations: 3.4.1 plastic type (P-FBGA) plastic-type classification is assigned to packages

29、which consist of resin substrate as interposer material (e.g. glass-epoxy, polyimid) 3.4.2 ceramic type (C-FBGA) ceramic-type classification is assigned to packages which consist of ceramic substrate as interposer material Page4 EN6019165:2001 BSI15November2001 4 601-19-6 5 IE:C0201(E) D E w S A w S

30、B v 4 NOTE 1 S y1 S y A 1 A S Seating plane NOTE 3 A1 A2 Even type Odd type A2 A1 S E nE nD A B e e ZE b S D ZD 123 A B C S x M A3 A4 B1 B2 B3 B4 A1 A2 NOTE 2 NOTE 2 IEC 1360/01 NOTE 1 Zone of a visible index on the top surface. NOTE 2 Datum A and B are the axes defined by the terminal positions ind

31、icated with datum targets. NOTE 3 Primary datum S and seating plane to be defined by the method of least squares of spherical crowns of land. Page5 EN6019165:2001 BSI15November2001061-19-6 5 IE:C0201(E) 5 Table 1 Group 1: Dimensions appropriate to mounting and interchangeability Limits to be observe

32、d Ref. Min. Nom. Max. Recommended values for the dimensions mm Note n X 1, 2 nD X nE X A X A max. = 1,20, 1,70, 2,00 Includes heat slug Includes package warpage and tilt A1 X X X Min. Nom. Max. at e = 0,80 0,35 0,40 0,45 at e = 0,65 0,28 0,33 0,38 at e = 0,50 0,20 0,25 0,30 at e = 0,40 0,15 0,20 0,2

33、5 b X X X Min. Nom. Max. at e = 0,80 0,45 0,50 0,55 at e = 0,65 0,35 0,40 0,45 at e = 0,50 0,25 0,30 0,35 at e = 0,40 0,20 0,25 0,30 D X At flanged type D = 4,0, 5,0, 6,0, 7,0, 8,0, 9,0, 10,0, 11,0, 12,0, 13,0, 14,0, 15,0, 16,0, Dimension range shows nominal value 17,0, 18,0, 19,0, 20,0, 21,0 at typ

34、e of real chip size D = from 3,1 to 21,0 E X at flanged type E = 4,0, 5,0, 6,0, 7,0, 8,0, 9,0, 10,0, 11,0, 12,0, 13,0, 14,0, 15,0, 16,0, 17,0, 18,0, 19,0, 20,0, 21,0 at type of real chip size E = from 3,1 to 21,0 Dimension range shows nominal value e X e = 0,80, 0,65, 0,50, 0,40 v X v = 0,15 Include

35、s burrs w X at e = 0,80 w = 0,20 at e = 0,65 w = 0,20 at e = 0,50 w = 0,20 at e = 0,40 w = 0,15 x X at e = 0,80 x = 0,08 at e = 0,65 x = 0,08 at e = 0,50 x = 0,05 at e = 0,40 x = 0,05 Page6 EN6019165:2001 BSI15November2001 6 601-19-6 5 IE:C0201(E) Table 1 (continued) Limits to be observed Ref. Min.

36、Nom. Max. Recommended values for the dimensions mm Note y X at e = 0,80 y = 0,10 at e = 0,65 y = 0,10 at e = 0,50 y = 0,08 at e = 0,40 y = 0,08 y1 X y1 = 0,2 NOTE 1 The values stipulated by the mathematical expression must be applied to the individual overall dimensional standards. NOTE 2 Symbol n r

37、efers to the total number of terminal positions. Table 2 Group 2: Dimensions appropriate to mounting and gauging Limits to be observed Ref. Min. Nom. Max. Recommended values for the dimensions mm Note b2 X at e = 0,80 b2 = 0,63 b2 = bmax. + x at e = 0,65 b2 = 0,53 at e = 0,50 b2 = 0,40 at e = 0,40 b

38、2 = 0,35 e X e = 0,80, 0,65, 0,50, 0,40 eD X eD = e (nD 1) eE X eD = e (nE 1) Table 3 Group 3: Dimensions appropriate to automated handling Limits to be observed Ref. Min. Nom. Max. Recommended values for the dimensions mm Note A X A max. = 1,20, 1,70, 2,00 Includes heat slug Includes package warpag

39、e and tilt D X D/E = 4,0, 5,0, 6,0, 7,0, 8,0, 9,0, 10,0, 11,0, 12,0, 13,0, 14,0, 15,0, 16,0, E X 17,0, 18,0, 19,0, 20,0, 21,0 y1 X y1 = 0,2 Table 4 Group 4: Dimensions for information only Limits to be observed Ref. Min. Nom. Max. Recommended values for the dimensions mm Note ZD X ZD = (D e (nD 1) /

40、 2 ZE X ZE = (E e (nE 1) / 2 Page7 EN6019165:2001 BSI15November2001061-19-6 5 IE:C0201(E) 7 Table 5 Dimensions and ball matrix e = 0,80 Maximum matrix family Maximum matrix 1 row family E D nD nE n ZD ZE nD nE n ZD ZE 4 4 4 4 16 0,80 0,80 3 3 9 1,20 1,20 5 5 5 5 25 0,90 0,90 4 4 16 1,30 1,30 6 6 7 7

41、 49 0,60 0,60 6 6 36 1,00 1,00 7 7 8 8 64 0,70 0,70 7 7 49 1,10 1,10 8 8 9 9 81 0,80 0,80 8 8 64 1,20 1,20 9 9 10 10 100 0,90 0,90 9 9 81 1,30 1,30 10 10 12 12 144 0,60 0,60 11 11 121 1,00 1,00 11 11 13 13 169 0,70 0,70 12 12 144 1,10 1,10 12 12 14 14 196 0,80 0,80 13 13 169 1,20 1,20 13 13 15 15 22

42、5 0,90 0,90 14 14 196 1,30 1,30 14 14 17 17 289 0,60 0,60 16 16 256 1,00 1,00 15 15 18 18 324 0,70 0,70 17 17 289 1,10 1,10 16 16 19 19 361 0,80 0,80 18 18 324 1,20 1,20 17 17 20 20 400 0,90 0,90 19 19 361 1,30 1,30 18 18 22 22 484 0,60 0,60 21 21 441 1,00 1,00 19 19 23 23 529 0,70 0,70 22 22 484 1,

43、10 1,10 20 20 24 24 576 0,80 0,80 23 23 529 1,20 1,20 21 21 25 25 625 0,90 0,90 24 24 576 1,30 1,30 e = 0,65 Maximum matrix family Maximum matrix 1 row family E D nD nE n ZD ZE nD nE n ZD ZE 4 4 5 5 25 0,700 0,700 4 4 16 1,025 1,025 5 5 7 7 49 0,550 0,550 6 6 36 0,875 0,875 6 6 8 8 64 0,725 0,725 7

44、7 49 1,050 1,050 7 7 10 10 100 0,575 0,575 9 9 81 0,900 0,900 8 8 11 11 121 0,750 0,750 10 10 100 1,075 1,075 9 9 13 13 169 0,600 0,600 12 12 144 0,925 0,925 10 10 14 14 196 0,775 0,775 13 13 169 1,100 1,100 11 11 16 16 256 0,625 0,625 15 15 225 0,950 0,950 12 12 17 17 289 0,800 0,800 16 16 256 1,12

45、5 1,125 13 13 19 19 361 0,650 0,650 18 18 324 0,975 0,975 14 14 20 20 400 0,825 0,825 19 19 361 1,150 1,150 15 15 22 22 484 0,675 0,675 21 21 441 1,000 1,000 16 16 23 23 529 0,850 0,850 22 22 484 1,175 1,175 17 17 25 25 625 0,700 0,700 24 24 576 1,025 1,025 18 18 27 27 729 0,550 0,550 26 26 676 0,87

46、5 0,875 19 19 28 28 784 0,725 0,725 27 27 729 1,050 1,050 20 20 30 30 900 0,575 0,575 29 29 841 0,900 0,900 21 21 31 31 961 0,750 0,750 30 30 900 1,075 1,075 Page8 EN6019165:2001 BSI15November2001 8 601-19-6 5 IE:C0201(E) e = 0,50 Maximum matrix family Maximum matrix 1 row family E D nD nE n ZD ZE n

47、D nE n ZD ZE 4 4 7 7 49 0,50 0,50 6 6 36 0,75 0,75 5 5 9 9 81 0,50 0,50 8 8 64 0,75 0,75 6 6 11 11 121 0,50 0,50 10 10 100 0,75 0,75 7 7 13 13 169 0,50 0,50 12 12 144 0,75 0,75 8 8 15 15 225 0,50 0,50 14 14 196 0,75 0,75 9 9 17 17 289 0,50 0,50 16 16 256 0,75 0,75 10 10 19 19 361 0,50 0,50 18 18 324

48、 0,75 0,75 11 11 21 21 441 0,50 0,50 20 20 400 0,75 0,75 12 12 23 23 529 0,50 0,50 22 22 484 0,75 0,75 13 13 25 25 625 0,50 0,50 24 24 576 0,75 0,75 14 14 27 27 729 0,50 0,50 26 26 676 0,75 0,75 15 15 29 29 841 0,50 0,50 28 28 784 0,75 0,75 16 16 31 31 961 0,50 0,50 30 30 900 0,75 0,75 17 17 33 33 1089 0,50 0,50 32 32 1024 0,75 0,75 18 18 35 35 1225 0,50 0,50 34 34 1156 0,75 0,75 19 19 37 37 1369 0,50 0,50 36 36 1296 0,75 0,75 20 20 39 39 1521 0,50 0,50 38 38 1444 0,75 0,75 21 21 41 41 1681 0,50 0,50 40 40 1600 0,75 0,75 e = 0,40 Maximum matrix family Maximum matrix 1