BS EN 60424-5-2009 Ferrite cores - Guide on the limits of surface irregularities - Part 5 Planar-cores《铁氧体磁芯 表面缺陷的限值指南 第5部分 平面磁芯》.pdf

1、raising standards worldwideNO COPYING WITHOUT BSI PERMISSION EXCEPT AS PERMITTED BY COPYRIGHT LAWBSI British StandardsWB9423_BSI_StandardColCov_noK_AW:BSI FRONT COVERS 5/9/08 12:55 Page 1Ferrite cores Guide on the limitsof surface irregularities Part 5: Planar-coresBS EN 60424-5:2009National forewor

2、dThis British Standard is the UK implementation of EN 60424-5:2009. It isidentical to IEC 60424-5:2009.The UK participation in its preparation was entrusted to Technical CommitteeEPL/51, Transformers, inductors, magnetic components and ferrite materials.A list of organizations represented on this co

3、mmittee can be obtained onrequest to its secretary.This publication does not purport to include all the necessary provisions of acontract. Users are responsible for its correct application. BSI 2009ISBN 978 0 580 60181 1ICS 29.100.10Compliance with a British Standard cannot confer immunity fromlegal

4、 obligations.This British Standard was published under the authority of the StandardsPolicy and Strategy Committee on 31 July 2009Amendments issued since publicationAmd. No. Date Text affectedBRITISH STANDARDBS EN 60424-5:2009EUROPEAN STANDARD EN 60424-5 NORME EUROPENNE EUROPISCHE NORM May 2009 CENE

5、LEC European Committee for Electrotechnical Standardization Comit Europen de Normalisation Electrotechnique Europisches Komitee fr Elektrotechnische Normung Central Secretariat: Avenue Marnix 17, B - 1000 Brussels 2009 CENELEC - All rights of exploitation in any form and by any means reserved worldw

6、ide for CENELEC members. Ref. No. EN 60424-5:2009 E ICS 29.100.10 English version Ferrite cores - Guide on the limits of surface irregularities - Part 5: Planar-cores (IEC 60424-5:2009) Noyaux ferrites - Guide relatif aux limites des irrgularits de surface - Partie 5: Noyaux planaires (CEI 60424-5:2

7、009) Ferritkerne - Leitfaden fr Grenzwerte von sichtbaren Beschdigungen der Kernoberflche - Teil 5: Planarkerne (IEC 60424-5:2009) This European Standard was approved by CENELEC on 2009-04-01. CENELEC members are bound to comply with the CEN/CENELEC Internal Regulations which stipulate the condition

8、s for giving this European Standard the status of a national standard without any alteration. Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the Central Secretariat or to any CENELEC member. This European Standard exists in three

9、official versions (English, French, German). A version in any other language made by translation under the responsibility of a CENELEC member into its own language and notified to the Central Secretariat has the same status as the official versions. CENELEC members are the national electrotechnical

10、committees of Austria, Belgium, Bulgaria, Cyprus, the Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, the Netherlands, Norway, Poland, Portugal, Romania, Slovakia, Slovenia, Spain, Sweden, Switzerland and the

11、 United Kingdom. EN 60424-5:2009 2 Foreword The text of document 51/947/FDIS, future edition 1 of IEC 60424-5, prepared by IEC TC 51, Magnetic components and ferrite materials, was submitted to the IEC-CENELEC parallel vote and was approved by CENELEC as EN 60424-5 on 2009-04-01. The following dates

12、 were fixed: latest date by which the EN has to be implemented at national level by publication of an identical national standard or by endorsement (dop) 2010-01-01 latest date by which the national standards conflicting with the EN have to be withdrawn (dow) 2012-04-01 Annex ZA has been added by CE

13、NELEC. _ Endorsement notice The text of the International Standard IEC 60424-5:2009 was approved by CENELEC as a European Standard without any modification. _ BS EN 60424-5:2009 3 EN 60424-5:2009 Annex ZA (normative) Normative references to international publications with their corresponding Europea

14、n publications The following referenced documents are indispensable for the application of this document. For dated references, only the edition cited applies. For undated references, the latest edition of the referenced document (including any amendments) applies. NOTE When an international publica

15、tion has been modified by common modifications, indicated by (mod), the relevant EN/HD applies. Publication Year Title EN/HD Year IEC 60424-1 - 1)Ferrite cores - Guide on the limits of surface irregularities - Part 1: General specification EN 60424-1 1999 2)IEC 62317-9 - 1)Ferrite cores - Dimensions

16、 - Part 9: Planar cores EN 62317-9 2006 2)1)Undated reference. 2)Valid edition at date of issue. BS EN 60424-5:2009IEC 60424-5Edition 1.0 2009-02INTERNATIONAL STANDARD Ferrite cores Guide on the limits of surface irregularities Part 5: Planar-cores INTERNATIONAL ELECTROTECHNICAL COMMISSION NICS 29.1

17、00.10 PRICE CODEISBN 2-8318-1032-6 Registered trademark of the International Electrotechnical Commission 2 60424-5 IEC:2009(E) CONTENTS FOREWORD.3 1 Scope.5 2 Normative references .5 3 Limits of surface irregularities.6 3.1 Chips and ragged edges6 3.1.1 Chips and ragged edges on the mating surfaces

18、(see Figures 1, 2 and 3)6 3.1.2 Chips and ragged edges on other surfaces7 3.2 Cracks.10 3.3 Flash.10 3.4 Pull-out .10 Figure 1 Chip location for planar EL-core.6 Figure 2 Chip location for low profile E-core.6 Figure 3 Chip location for low profile ER-core 6 Figure 4 Cracks and pull-out location for

19、 planar EL-core 10 Figure 5 Cracks and pull-out location for low profile E-core11 Figure 6 Cracks and pull-out location for low profile ER-core .11 Figure 7 Reference dimensions for EL-core .11 Figure 8 Reference dimensions for E-core .12 Figure 9 Reference dimensions for ER-core.13 Table 1 Allowabl

20、e areas of chips in mm2for planar EL-core.7 Table 2 Allowable areas of chips in mm2for low profile E-core 8 Table 3 Allowable areas of chips in mm2for low profile ER-core 8 Table 4 Area and length reference for visual inspection .9 Table 5 Limits of cracks for planar EL-core 12 Table 6 Limits of cra

21、cks for low profile E-core13 Table 7 Limits of cracks for low profile ER-core .14 BS EN 60424-5:200960424-5 IEC:2009(E) 3 INTERNATIONAL ELECTROTECHNICAL COMMISSION _ FERRITE CORES GUIDE ON THE LIMITS OF SURFACE IRREGULARITIES Part 5: Planar-cores FOREWORD 1) The International Electrotechnical Commis

22、sion (IEC) is a worldwide organization for standardization comprising all national electrotechnical committees (IEC National Committees). The object of the IEC is to promote international co-operation on all questions concerning standardization in the electrical and electronic fields. To this end an

23、d in addition to other activities, IEC publishes International Standards, Technical Specifications, Technical Reports, Publicly Available Specifications (PAS) and Guides (hereafter referred to as “IEC Publication(s)“). Their preparation is entrusted to technical committees; any IEC National Committe

24、e interested in the subject dealt with may participate in this preparatory work. International, governmental and non-governmental organizations liaising with the IEC also participate in this preparation. IEC collaborates closely with the International Organization for Standardization (ISO) in accord

25、ance with conditions determined by agreement between the two organizations. 2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international consensus of opinion on the relevant subjects since each technical committee has representation from all inte

26、rested IEC National Committees. 3) IEC Publications have the form of recommendations for international use and are accepted by IEC National Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC Publications is accurate, IEC cannot be held respons

27、ible for the way in which they are used or for any misinterpretation by any end user. 4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications transparently to the maximum extent possible in their national and regional publications. Any divergence

28、between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in the latter. 5) IEC provides no marking procedure to indicate its approval and cannot be rendered responsible for any equipment declared to be in conformity with an IEC Publication. 6) All

29、 users should ensure that they have the latest edition of this publication. 7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and members of its technical committees and IEC National Committees for any personal injury, property damage or

30、 other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC Publications. 8) Attention is drawn to the Normative references cited in this publicati

31、on. Use of the referenced publications is indispensable for the correct application of this publication. 9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of patent rights. IEC shall not be held responsible for identifying any or all such p

32、atent rights. International Standard IEC 60424-5 has been prepared by IEC technical committee 51: Magnetic components and ferrite materials. The text of this standard is based on the following documents: FDIS Report on voting 51/947/FDIS 51/950/RVD Full information on the voting for the approval of

33、this standard can be found in the report on voting indicated in the above table. This publication has been drafted in accordance with the ISO/IEC Directives, Part 2. A list of all parts of the IEC 60424 series, under the general title Ferrite cores Guide on the limits of surface irregularities, can

34、be found on the IEC website. BS EN 60424-5:2009 4 60424-5 IEC:2009(E) The committee has decided that the contents of this publication will remain unchanged until the maintenance result date indicated on the IEC web site under “http:/webstore.iec.ch“ in the data related to the specific publication. A

35、t this date, the publication will be reconfirmed, withdrawn, replaced by a revised edition, or amended. A bilingual version of this publication may be issued at a later date. BS EN 60424-5:200960424-5 IEC:2009(E) 5 FERRITE CORES GUIDE ON THE LIMITS OF SURFACE IRREGULARITIES Part 5: Planar-cores 1 Sc

36、ope This part of IEC 60424 gives guidance on allowable limits of surface irregularities applicable to planar-cores in accordance with the relevant generic specification defined in IEC 60424-1. The relations between the main dimensions of planar E-, ER- and EL-cores differ from those of standard core

37、s. For example, the width of planar cores is larger while the total height is much smaller. Also the thickness of the legs is in most cases smaller than compared to standard cores. Therefore the concept of fixed reference dimensions to determine the length of crack limits yield crack lengths which a

38、re not acceptable for this type of core. This part of IEC 60424 follows another concept which relates the crack length to dimensions of the surface on which the crack occurs. Also the concept to determine the maximum area of chips based on the total mating surface fails in the case of planar cores.

39、The outer legs of planar cores are much thinner than those of standard cores which makes overlapping and gluing much more difficult. A single chip of maximum size on the outer leg may risk the functionality of the core set. Therefore this standard uses as a reference the mating surface on which the

40、chip occurs. Windings of planar cores are often PCBs which are glued to the inner surfaces of the planar core. For this reason the inner surfaces of the planar cores need to have a better quality than the inner surfaces of standard cores. This was taken into account by reducing the maximum allowable

41、 area of pull outs in the inner surfaces. This standard is considered as a sectional specification useful in the negotiation between ferrite core manufacturers and users about surface irregularities. 2 Normative references The following referenced documents are indispensable for the application of t

42、his document. For dated references, only the edition cited applies. For undated references, the latest edition of the referenced document (including any amendments) applies. IEC 60424-1, Ferrite cores Guide on the limits of surface irregularities Part 1: General specification IEC 62317-9, Ferrite co

43、res Dimensions Part 9: Planar-cores BS EN 60424-5:2009 6 60424-5 IEC:2009(E) 3 Limits of surface irregularities 3.1 Chips and ragged edges 3.1.1 Chips and ragged edges on the mating surfaces (see Figures 1, 2 and 3) C1 Mating surfaces Ragged edges C1 IEC 360/09 Figure 1 Chip location for planar EL-c

44、ore C2 Mating surfaces Ragged edges C1 C1 IEC 361/09 Figure 2 Chip location for low profile E-core Wire slot area C2 Mating surfaces Ragged edges C1 C1 IEC 362/09 Figure 3 Chip location for low profile ER-core Areas of the chips located on the mating surfaces (C1 and C1 irregularities in Figures 1,

45、2 and 3) shall not exceed the following limits: the cumulative area of the chips shall be less than 4 % of the relevant mating surface. The mating surface of each outer leg and centre post is considered separately; the allowable areas are rounded to the figures in Table 4 (Area and length reference

46、for visual inspection) and the minimum allowable area is taken as 0,5 mm2to be distinguishable to the naked eye; BS EN 60424-5:200960424-5 IEC:2009(E) 7 the total area of all chips on all mating surfaces shall not exceed the value given for “overall chipping on the mating surface” in Tables 1, 2 or

47、3; the total length of the ragged edges shall be less than 25 % of the perimeter of the relevant mating surface. 3.1.2 Chips and ragged edges on other surfaces the allowable chipping areas are doubled as compared to the limits for the whole mating surfaces (see Table 1 for planar EL-corers, Table 2

48、for low profile E-cores, Table 3 for low profile ER-cores); the total length of the ragged edges shall be less than 25 % of the perimeter of the smaller adjoining surface; chips and ragged edges are not acceptable on the ridge of the clamping recess area; chips and ragged edges are not acceptable on

49、 the inner edges of wire slot area. (C2 irregularity in Figures 2 and 3) The core sizes given in Tables 1, 2 and 3 correspond to the cores defined in IEC 62317-9, and area and length reference for visual inspection are given in Table 4. Table 1 Allowable areas of chips in mm2for planar EL-core Core size Chipping on mating surface of one outer leg Chipping on mating surface of centre post Ov