BS EN 61523-2-2002 Delay and power calculation standards - Pre-layout delay calculation specification for CMOS ASIC libraries《延迟计算和功率计算标准 CMOS集成电路子程序库 预布局延迟计算规范》.pdf

1、Licensed Copy: Wang Bin, ISO/Exchange China Standards Information Centre, 21 January 2003, Uncontrolled Copy, (c) BSIBRITISH STANDARD BS EN 61523-2:2002 Delay and power calculation standards Part 2: Pre-layout delay calculation specification for CMOS ASIC libraries The European Standard EN 61523-2:2

2、002 has the status of a British Standard ICS 35.240.50 Licensed Copy: Wang Bin, ISO/Exchange China Standards Information Centre, 21 January 2003, Uncontrolled Copy, (c) BSIBS EN 61523-2:2002 This British Standard, having been prepared under the direction of the Electrotechnical Sector Policy and Str

3、ategy Committee, was published under the authority of the Standards Policy and Strategy Committee on 27 September 2002 BSI 27 September 2002 ISBN 0 580 40460 9 National foreword This British Standard is the official English language version of EN 61523-2:2002. It is identical with IEC 61523-2:2002.

4、The UK participation in its preparation was entrusted to Technical Committee GEL/93, Design automation, which has the responsibility to: A list of organizations represented on this committee can be obtained on request to its secretary. Cross-references The British Standards which implement internati

5、onal or European publications referred to in this document may be found in the BSI Catalogue under the section entitled “International Standards Correspondence Index”, or by using the “Search” facility of the BSI Electronic Catalogue or of British Standards Online This publication does not purport t

6、o include all the necessary provisions of a contract. Users are responsible for its correct application. Compliance with a British Standard does not of itself confer immunity from legal obligations. aid enquirers to understand the text; present to the responsible European committee any enquiries on

7、the interpretation, or proposals for change, and keep the UK interests informed; monitor related international and European developments and promulgate them in the UK. Summary of pages This document comprises a front cover, an inside front cover, the EN title page, pages 2 to 38, an inside back cove

8、r and a back cover. The BSI copyright date displayed in this document indicates when the document was last issued. Amendments issued since publication Amd. No. Date Comments Licensed Copy: Wang Bin, ISO/Exchange China Standards Information Centre, 21 January 2003, Uncontrolled Copy, (c) BSIEUROPEAN

9、STANDARD EN 61523-2 NORME EUROPENNE EUROPISCHE NORM August 2002 CENELEC European Committee for Electrotechnical Standardization Comit Europen de Normalisation Electrotechnique Europisches Komitee fr Elektrotechnische Normung Central Secretariat: rue de Stassart 35, B - 1050 Brussels 2002 CENELEC - A

10、ll rights of exploitation in any form and by any means reserved worldwide for CENELEC members. Ref. No. EN 61523-2:2002 E ICS 35.240.50 English version Delay and power calculation standards Part 2: Pre-layout delay calculation specification for CMOS ASIC libraries (IEC 61523-2:2002) Calcul de puissa

11、nce et de dlai Partie 2 : Spcification du calcul du dlai de pr-implantation pour les librairies ASIC CMOS (CEI 61523-2:2002) Berechnung von Verzgerung und Leistungsaufnahme beim Entwurf von Chips Teil 2: Vorgezogene Berechnung der Verzgerung fr CMOS-ASIC-Bibliotheken (IEC 61523-2:2002) This European

12、 Standard was approved by CENELEC on 2002-07-01. CENELEC members are bound to comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration. Up-to-date lists and bibliographical references co

13、ncerning such national standards may be obtained on application to the Central Secretariat or to any CENELEC member. This European Standard exists in three official versions (English, French, German). A version in any other language made by translation under the responsibility of a CENELEC member in

14、to its own language and notified to the Central Secretariat has the same status as the official versions. CENELEC members are the national electrotechnical committees of Austria, Belgium, Czech Republic, Denmark, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Luxembourg, Malta,

15、Netherlands, Norway, Portugal, Slovakia, Spain, Sweden, Switzerland and United Kingdom. Licensed Copy: Wang Bin, ISO/Exchange China Standards Information Centre, 21 January 2003, Uncontrolled Copy, (c) BSIForeword The text of document 93/151/FDIS, future edition 1 of IEC 61523-2, prepared by IEC TC

16、93, Design automation, was submitted to the IEC-CENELEC parallel vote and was approved by CENELEC as EN 61523-2 on 2002-07-01. The ASIC Library Representation Working Group of EIAL EDA Technical Committee also participated in the preparation of this standard. This standard is a revision of the EIAJ

17、1)document: ASIC Library Representation (ALR):1994. The following dates were fixed: latest date by which the EN has to be implemented at national level by publication of an identical national standard or by endorsement (dop) 2003-04-01 latest date by which the national standards conflicting with the

18、 EN have to be withdrawn (dow) 2005-07-01 Annexes designated “normative“ are part of the body of the standard. Annexes designated “informative“ are given for information only. In this standard, annex ZA is normative and annexes A to F are informative. Annex ZA has been added by CENELEC. _ Endorsemen

19、t notice The text of the International Standard IEC 61523-2:2002 was approved by CENELEC as a European Standard without any modification. _1)Electronic Industries Association of Japan. Page2 EN615232:2002Licensed Copy: Wang Bin, ISO/Exchange China Standards Information Centre, 21 January 2003, Uncon

20、trolled Copy, (c) BSICONTENTS 1Scope and object 4 2Normative references.4 3Relations with other companion standards activities5 4 Terms and definitions.5 5Pre-layout delay calculation method for CMOS ASIC libraries .6 Annex A (informative) Four points interpolation.14 Annex B (informative) Three pon

21、ts interpolation16 Annex C (informative) Selection method of interpolation plane.19 Annex D (informative) Theoretical accuracy comparison between two interpolation methods.24 Annex E (informative) Application example30 Annex F (informative) Example of Cn, Ts, Tpd tables by delay calculation language

22、34 Page3 EN615232:2002 Annex ZA (normative) Normative references to international publications with their corresponding European publications . 38 Licensed Copy: Wang Bin, ISO/Exchange China Standards Information Centre, 21 January 2003, Uncontrolled Copy, (c) BSI“#$%29?C?24?; C;3!,D)0!%0/,!9?E323?7

23、A !“#!“#$% ; #?#E(#F.2)3#/)2/52)(#)-2“ ) #-2“ Page4 EN615232:2002Licensed Copy: Wang Bin, ISO/Exchange China Standards Information Centre, 21 January 2003, Uncontrolled Copy, (c) BSIM“#4%5,0#(3 “ $%.#45(-5(#40#(%.#+.2)3#/)2/52)(4,#“ O“#8%./3 # $%0 first value second value,second value of Si = first

24、value of Si+1, Page8 EN615232:2002Licensed Copy: Wang Bin, ISO/Exchange China Standards Information Centre, 21 January 2003, Uncontrolled Copy, (c) BSI second value of Foj = first value of Foj+1,first value effective value second value,Cnij is real value, unit is pF or fF. 5.2.1.2 Net capacitance( C

25、nE ) estimation ruleThe Net capacitance estimation (CnE) is specified below. If the size is ranged in Si and the fanout is ranged in Fojt h e nCnE = Cnij . (1)If the size is less than the first value of S1, then set i to 1.If the size is greater than or equal to the second vale of SM, then set i to

26、M.If the fanout is less than the first value of Fo1, then set j to 1.If the fanout is greater than or equal to the second value of FoN,then set j to N.Then apply it to function (1). 5.2.2 Input slew rate calculationInput slew rate is calculated by linear interpolation shown in figure 3.TimeS N S i +

27、 1 S 0S i S 1 C 1 C i C L 0 C i + 1 C N C a p . Figure 3. Example of input slew rate calculation 5.2.2.1 Ts table specificationA Ts table is a one dimensional matrix for each transient timing group.(See F.2) The index( Ci) is the capacitance of the net which includes the input of the target gate, Th

28、e value( Si) is the characterized input slew ratew h e r e2 i N (N is effective maximum number of capacitance values used,Ci has 1 real value of capacitance, unit is pF or fF,0 Ci Ci+1,Si has 1 real value of time, unit is ns. Page9 EN615232:2002Licensed Copy: Wang Bin, ISO/Exchange China Standards I

29、nformation Centre, 21 January 2003, Uncontrolled Copy, (c) BSI5.2.2.2 Input slew rate( Ts0) calculation ruleTo calculate input slew rate by Ts table, the linear interpolation method will be applied between Ci and Ci+1. If target input capacitance( C0) is ranged between Ci and Ci+1 then Ts0 = a C0 +

30、b (2) where a = (Si+1 Si) (Ci+1 Ci) b = (Ci+1 Si Ci Si+1) (Ci+1 Ci).If target input capacitance is less than C1, then set i to 1. If target input capacitance is greater than CN, then set i to N-1. Then apply it to function of (2). 5.2.3 Port to Port propagation delay time calculationPort to port del

31、ay is calculated using as Tpd table ,shown in Figure 4, using either a linear or a bilinear interpolation method.Figure 4. Example of propagation delay time calculation 5.2.3.1 Tpd table specificationTpd table is a two dimensional matrix for each transient timing group.(See F.3) Tpdi+1j+1 Tpdi+1j Tp

32、dij+1 T s 1 T s i T s 0 T s i + 1 T s M T i m e Tpd0 Time Cl1 Clj Cl0 Clj+1 ClN Capacitance Page10 EN615232:2002Licensed Copy: Wang Bin, ISO/Exchange China Standards Information Centre, 21 January 2003, Uncontrolled Copy, (c) BSIThe 1st index ( Tsi) is input slew rate , The 2nd index( Clj) is load c

33、apacitance of output of gate, The value ( Tpdij) is characterized propagation delay time,w h e r e 2 i M (M is effective maximum number of input slew rates used), Tsi has 1 real value of time, unit is ns, 0 Tsi Tsi+1, 2 j N ( N is effective maximum number of load capacitance values ofgate output use

34、d), Clj has 1 real value of capacitance, unit is pF or fF, 0 Clj Clj+1, Tpdij has 1 real value of time, unit is ns, Tpdij Tpdi+1j, Tpdij+1 Tpdi+1j+1. 5.2.3.2 Selection rule of 4 pointsTo calculate port to port propagation delay time by Tpd table, both linear and bilinearinterpolation method are appl

35、ied among 4 points .(Tpdij,Tpdi+1j,Tpdij+1,Tpdi+1j+1) as shown in Figure 4.If calculated Ts0 is ranged between Tsi and Tsi+1 andif target load capacitance( CL1) is ranged between Clj and Clj+1,t h e n s e l e c tTpdij,Tpdi+1j,Tpdij+1,Tpdi+1j+1. If Ts0 is less than Ts1, set i to 1. If Ts0 is greater

36、than TsM, set i to M-1. If CL1 is less than Cl1, set j to 1. If CL1 is greater than ClN, set j to N-1. Then select Tpdij,Tpdi+1j,Tpdij+1,Tpdi+1j+1. 5.2.3.3 Propagation delay time( Tpd0) approximationTwo methods are specified here.One is to solve bilinear interpolation (Z = a X + b Y + c X Y + d).See

37、 Annex A in details.Another method is the linear interpolation based on 3 points which are selected from4 points shown in figure 5. (See Annex F.4 for detail interpolation example) 5.2.3.3.1 Selection rule of 3 pointsTpd is slowly increasing convex function with negative second derivatives.In this case, 3 point linear approximation is more accurate than bilinear interpolation Page11 EN615232:2002Licensed Copy: Wang Bin, ISO/Exchange China Standards Information Centre, 21 January 2003, Uncontrolled Copy, (c) BSI