BS EN 61691-2-2002 Design automation - Behavioural languages - VHDL multilogic system for model interoperability《设计自动化 行为语言 模型互操作性的VHDL多种逻辑系统》.pdf

1、BRITISH STANDARD BS EN 61691-2:2001 IEC 61691-2:2001 Behavioural languages Part 2: VHDL multilogic system for model interoperability The European Standard EN 61691-2:2001 has the status of a British Standard ICS 35.240.50 NO COPYING WITHOUT BSI PERMISSION EXCEPT AS PERMITTED BY COPYRIGHT LAWBS EN 61

2、691-2:2001 This British Standard, having been prepared under the direction of the Electrotechnical Sector Policy and Strategy Committee, was published under the authority of the Standards Policy and Strategy Committee on 2 April 2002 BSI 2 April 2002 ISBN 0 580 39266 X National foreword This British

3、 Standard is the official English language version of EN 61691-2:2001. It is identical with IEC 61691-2:2001. The UK participation in its preparation was entrusted to Technical Committee GEL/93, Design automation, which has the responsibility to: A list of organizations represented on this committee

4、 can be obtained on request to its secretary. From 1 January 1997, all IEC publications have the number 60000 added to the old number. For instance, IEC 27-1 has been renumbered as IEC 60027-1. For a period of time during the change over from one numbering system to the other, publications may conta

5、in identifiers from both systems. Cross-references The British Standards which implement international or European publications referred to in this document may be found in the BSI Standards Catalogue under the section entitled “International Standards Correspondence Index”, or by using the “Find” f

6、acility of the BSI Standards Electronic Catalogue. A British Standard does not purport to include all the necessary provisions of a contract. Users of British Standards are responsible for their correct application. Compliance with a British Standard does not of itself confer immunity from legal obl

7、igations. aid enquirers to understand the text; present to the responsible international/European committee any enquiries on the interpretation, or proposals for change, and keep the UK interests informed; monitor related international and European developments and promulgate them in the UK. Summary

8、 of pages This document comprises a front cover, an inside front cover, the EN title page, the EN foreword page, the IEC title page, pages 2 to 23 and a back cover. The BSI copyright date displayed in this document indicates when the document was last issued. Amendments issued since publication Amd.

9、 No. Date CommentsEUROPEAN STANDARD EN 61691-2 NORME EUROPENNE EUROPISCHE NORM December 2001 CENELEC European Committee for Electrotechnical Standardization Comit Europen de Normalisation Electrotechnique Europisches Komitee fr Elektrotechnische Normung Central Secretariat: rue de Stassart 35, B - 1

10、050 Brussels 2001 CENELEC - All rights of exploitation in any form and by any means reserved worldwide for CENELEC members. Ref. No. EN 61691-2:2001 E ICS 35.240.50 English version Behavioural languages Part 2: VHDL multilogic system for model interoperability (IEC 61691-2:2001) Langages relatifs au

11、 comportement Partie 2: Systme multilogique en VHDL permettant linteroprabilit des modles (CEI 61691-2:2001) Verhaltensebenensprache Teil 2: System fr mehrwertige Logik fr das VHDL-Interoperabilittsmodell (IEC 61691-2:2001) This European Standard was approved by CENELEC on 2001-09-01. CENELEC member

12、s are bound to comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration. Up-to-date lists and bibliographical references concerning such national standards may be obtained on application

13、 to the Central Secretariat or to any CENELEC member. This European Standard exists in three official versions (English, French, German). A version in any other language made by translation under the responsibility of a CENELEC member into its own language and notified to the Central Secretariat has

14、 the same status as the official versions. CENELEC members are the national electrotechnical committees of Austria, Belgium, Czech Republic, Denmark, Finland, France, Germany, Greece, Iceland, Ireland, Italy, Luxembourg, Malta, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland and United Kin

15、gdom.EN 61691-2:2001 - 2 - Foreword The text of document 93/130/FDIS, future edition 1 of IEC 61691-2, prepared by IEC TC 93, Design automation, was submitted to the IEC-CENELEC parallel vote and was approved by CENELEC as EN 61691-2 on 2001-09-01. The following dates were fixed: latest date by whic

16、h the EN has to be implemented at national level by publication of an identical national standard or by endorsement (dop) 2002-06-01 latest date by which the national standards conflicting with the EN have to be withdrawn (dow) 2004-09-01 This standard is based on IEEE Std 1164:1993, Multivalue logi

17、c system for VHDL model interoperability. _ Endorsement notice The text of the International Standard IEC 61691-2:2001 was approved by CENELEC as a European Standard without any modification. _ EN616912:2001INTERNATIONAL STANDARD IEC 61691-2 First edition 2001-06 Behavioural languages Part 2: VHDL m

18、ultilogic system for model interoperability Reference number IEC 61691-2:2001(E) EN616912:2001BEHAVIOURAL LANGUAGES - Part 2: VHDL multilogic system for model interoperatibility 1. Overview 1.1 Scope This standard is embodied in the Std_logic_1164 package package body along with this clause 1 docume

19、ntation. The information annex AA is a guide to users and is not part of this standard, but suggests ways in which one might use 1.2 Conformance with this standard The following conformance rules shall apply as they a) No modifications shall be made to the package declaration b) The Std_logic_1164 p

20、ackage body represents the formal Std_logic_1164 package declaration. Implementers of this package body as it is; or they may choose to implement to the user. Users shall not implement a semantic that 2. Std_logic_1164 package declaration - - Title : Std_logic_1164 multivalue logic system - Library

21、: This package shall be compiled into a library - : symbolically named IEEE. - : - Developers: IEEE model standards group (par 1164) - Purpose : This packages defines a standard for designers - : to use in describing the - : used in VHDL modeling. - : )E(1002:CEI 2-19616 - 4 - 4egaP EN616912:2001 20

22、02lirpA2ISB Page2 EN616912:2001 BSI2April2002- Limitation: The logic system defined in this package may - : be insufficient for modeling switched - : since such a requirement is out of the - : effort. Furthermore, mathematics, primitives, - : timing standards, etc. are considered - : issues in relat

23、ion to this package and - : beyond the scope of this effort. - : - Note : No declarations or definitions shall be - : or excluded from, this package. The - : defines the types, subtypes, and - : Std_logic_1164. The Std_logic_1164 - : considered the formal definition of the - : this package. Tool dev

24、elopers may - : the package body in the most efficient - : to them. - : - - modification history : - - version | mod. date:| - v4.200 | 01/02/92 | - PACKAGE Std_logic_1164 IS- logic state system (unresolved)TYPE std_ulogic IS ( U, - UninitializedX, - Forcing Unknown0, - Forcing 01, - Forcing 1Z, - H

25、igh ImpedanceW, - Weak UnknownL, - Weak 0H, - Weak 1- - Dont care);- unconstrained array of std_ulogic for use with the TYPE std_ulogic_vector IS ARRAY ( NATURAL RANGE ) OF )E(1002:CEI 2-19616 - 5 - 5egaP EN616912:2001 2002lirpA2ISB Page3 EN616912:2001 BSI2April2002 - common subtypesSUBTYPE X01 IS r

26、esolved std_ulogic RANGE SUBTYPE X01Z IS resolved std_ulogic RANGE Z) SUBTYPE UX01 IS resolved std_ulogic RANGE 1) SUBTYPE UX01Z IS resolved std_ulogic RANGE 1, Z)- overloaded logical operatorsFUNCTION “and” ( l : std_ulogic; r : FUNCTION “nand” ( l : std_ulogic; r : FUNCTION “or” ( l : std_ulogic;

27、r : FUNCTION “nor” ( l : std_ulogic; r : FUNCTION “xor” ( l : std_ulogic; r : FUNCTION “xnor” ( l : std_ulogic; r : FUNCTION “not” ( l : std_ulogic - vectorized overloaded logical operatorsFUNCTION “and” ( l, r : std_logic_vector ) FUNCTION “and” ( l, r : std_ulogic_vector ) FUNCTION “nand” ( l, r :

28、 std_logic_vector ) FUNCTION “nand” ( l, r : std_ulogic_vector ) FUNCTION “or” ( l, r : std_logic_vector ) FUNCTION “or” ( l, r : std_ulogic_vector ) FUNCTION “nor” ( l, r : std_logic_vector ) FUNCTION “nor” ( l, r : std_ulogic_vector ) FUNCTION “xor” ( l, r : std_logic_vector ) FUNCTION “xor” ( l,

29、r : std_ulogic_vector ) - - Note : The declaration and implementation of the “ - specifically commented until a time at which the VHDL - officially adopted as containing such a function. At - the following comments may be removed along with this - further “official” balloting of this - the intent of

30、 this effort to provide such a function - available in the VHDL standard. - - FUNCTION “xnor” ( l, r : std_logic_vector ) - FUNCTION “xnor” ( l, r : std_ulogic_vector ) FUNCTION “not” ( l : std_logic_vector ) FUNCTION “not” ( l : std_ulogic_vector ) - conversion functionsFUNCTION To_bit ( s : std_ul

31、ogic; xmap : FUNCTION To_bitvector ( s : std_logic_vector ; xmap : BIT_VECTOR;FUNCTION To_bitvector ( s : std_ulogic_vector; xmap : BIT_VECTOR;FUNCTION To_StdULogic ( b : BIT ) FUNCTION To_StdLogicVector ( b : BIT_VECTOR ) FUNCTION To_StdLogicVector ( s : std_ulogic_vector ) RETURN std_logic_vector;

32、FUNCTION To_StdULogicVector ( b : BIT_VECTOR ) RETURN std_ulogic_vector;FUNCTION To_StdULogicVector ( s : std_logic_vector ) RETURN std_ulogic_vector;)E(1002:CEI 2-19616 - 6 - 6egaP EN616912:2001 2002lirpA2ISB Page4 EN616912:2001 BSI2April2002 - strength strippers and type convertersFUNCTION To_X01

33、( s : std_logic_vector ) RETURN FUNCTION To_X01 ( s : std_ulogic_vector ) RETURN FUNCTION To_X01 ( s : std_ulogic ) RETURN X01;FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN FUNCTION To_X01 ( b : BIT ) RETURN X01;FUNCTION To_X01Z ( s : std_logic_vector ) RETURN F

34、UNCTION To_X01Z ( s : std_ulogic_vector ) RETURN FUNCTION To_X01Z ( s : std_ulogic ) RETURN X01Z;FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN FUNCTION To_X01Z ( b : BIT ) RETURN X01Z;FUNCTION To_UX01 ( s : std_logic_vector ) RETURN FUNCTION To_UX01 ( s : std_

35、ulogic_vector ) RETURN FUNCTION To_UX01 ( s : std_ulogic ) RETURN UX01;FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN FUNCTION To_UX01 ( b : BIT ) RETURN UX01;- edge detectionFUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN;FUNCTION falling_edge (SIG

36、NAL s : std_ulogic) RETURN BOOLEAN;- object contains an unknownFUNCTION Is_X ( s : std_ulogic_vector ) RETURN BOOLEAN;FUNCTION Is_X ( s : std_logic_vector ) RETURN BOOLEAN;FUNCTION Is_X ( s : std_ulogic ) RETURN BOOLEAN; END Std_logic_1164; 3. Std_logic_1164 package body - - - Title : Std_logic_1164

37、 multivalue logic system - Library : This package shall be compiled into a library - : symbolically named IEEE. - : - Developers: IEEE model standards group (par 1164) - Purpose : This package defines a standard for designers - : to use in describing the interconnection - : used in VHDL modeling. -

38、: - Limitation: The logic system defined in this package may - : be insufficient for modeling switched - : since such a requirement is out of the - : effort. Furthermore, mathematics, primitives, - : timing standards, etc., are considered - : issues in relation to this package and )E(1002:CEI 2-1961

39、6 - 7 - 7egaP EN616912:2001 2002lirpA2ISB Page5 EN616912:2001 BSI2April2002- : beyond the scope of this effort. - : - Note : No declarations or definitions shall be - : or excluded from this package. The “ - : defines the types, subtypes and declarations of - : Std_logic_1164. The Std_logic_1164 - :

40、 considered the formal definition of the - : this package. Tool developers may choose - : the package body in the most efficient - : to them. - : - - modification history : - - version | mod. date:| - v4.200 | 01/02/91 | - PACKAGE BODY Std_logic_1164 IS- local typesTYPE stdlogic_1d IS ARRAY (std_ulo

41、gic) OF std_ulogic;TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) - resolution functionCONSTANT resolution_table : stdlogic_table := (- - | U X 0 1 Z W L H - - ( U, U, U, ( U, X, X, ( U, X, 0, ( U, X, X, ( U, X, 0, ( U, X, 0, ( U, X, 0, ( U, X, 0, ( U, X, X, );FUNCTION resolved ( s : std_ulogi

42、c_vector ) RETURN VARIABLE result : std_ulogic := Z; - BEGIN- the test for a single driver is essential; - loop would return X for a single - would conflict with the value of a single - signal.IF (sLENGTH = 1) THEN RETURN s (sLOW);ELSEFOR i IN sRANGE LOOPresult := resolution_table (result, s(i);END

43、LOOP;END IF; )E(1002:CEI 2-19616 - 8 - 8egaP EN616912:2001 2002lirpA2ISB Page6 EN616912:2001 BSI2April2002 RETURN result;END resolved;-tables for logical operations-truth table for “and” functionCONSTANT and_table : stdlogic_table : = (- - | U X 0 1 Z W L H - - -( U, U, 0, ( U, X, 0, ( 0, 0, 0, ( U,

44、 X, 0, ( U, X, 0, ( U, X, 0, ( 0, 0, 0, ( U, X, 0, ( U, X, 0, );- truth table for “or” functionCONSTANT or_table : stdlogic_table := (- - | U X 0 1 Z W L H - - -( U, U, U, ( U, X, X, ( U, X, 0, ( 1, 1, 1, ( U, X, X, ( U, X, X, ( U, X, 0, ( 1 1, 1, ( U, X, X, );- truth table for “xor” functionCONSTAN

45、T xor_table : stdlogic_table := (- - | U X 0 1 Z W L H - - -( U, U, U, ( U, X, X, ( U, X, 0, ( U, X, 1, ( U, X, X, ( U, X, X, ( U, X, 0, ( U, X, 1, ( U, X, X, );- truth table for “not” functionCONSTANT not_table: stdlogic_1d :=- - | U X 0 1 Z W L H - | )E(1002:CEI 2-19616 - 9 - 9egaP EN616912:2001 2

46、002lirpA2ISB Page7 EN616912:2001 BSI2April2002 - -( U, X, 1, 0, - overloaded logical operators ( with optimizing hints )FUNCTION “and” ( l : std_ulogic; r : BEGINRETURN (and_table(l, r);END “and”;FUNCTION “nand” ( l : std_ulogic; r : BEGINRETURN (not_table ( and_table(l, r);END “nand”;FUNCTION “or” ( l : std_ulogic; r : BEGINRETURN (or_table(l, r);END “or”;FU