BS EN 62418-2010 Semiconductor devices Metallization stress void test《半导体器件 金属化应力空隙试验》.pdf

1、raising standards worldwideNO COPYING WITHOUT BSI PERMISSION EXCEPT AS PERMITTED BY COPYRIGHT LAWBSI Standards PublicationSemiconductor devices Metallization stress void testBS EN 62418:2010National forewordThis British Standard is the UK implementation of EN 62418:2010. It is identical to IEC 62418

2、:2010.The UK participation in its preparation was entrusted to Technical CommitteeEPL/47, Semiconductors.A list of organizations represented on this committee can be obtained onrequest to its secretary.This publication does not purport to include all the necessary provisions of acontract. Users are

3、responsible for its correct application. BSI 2010ISBN 978 0 580 62610 4ICS 31.080.01Compliance with a British Standard cannot confer immunity fromlegal obligations.This British Standard was published under the authority of the StandardsPolicy and Strategy Committee on 31 August 2010.Amendments issue

4、d since publicationAmd. No. Date Text affectedBRITISH STANDARDBS EN 62418:2010EUROPEAN STANDARD EN 62418 NORME EUROPENNE EUROPISCHE NORM July 2010 CENELEC European Committee for Electrotechnical Standardization Comit Europen de Normalisation Electrotechnique Europisches Komitee fr Elektrotechnische

5、Normung Management Centre: Avenue Marnix 17, B - 1000 Brussels 2010 CENELEC - All rights of exploitation in any form and by any means reserved worldwide for CENELEC members. Ref. No. EN 62418:2010 E ICS 31.080 English version Semiconductor devices - Metallization stress void test (IEC 62418:2010) Di

6、spositifs semi-conducteurs - Essai sur les cavits dues aux contraintes de la mtallisation (CEI 62418:2010) Halbleiterbauelemente - Prfverfahren zur Metallisierungs-Stressmigration (IEC 62418:2010) This European Standard was approved by CENELEC on 2010-07-01. CENELEC members are bound to comply with

7、the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration. Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the Central Secretariat

8、 or to any CENELEC member. This European Standard exists in three official versions (English, French, German). A version in any other language made by translation under the responsibility of a CENELEC member into its own language and notified to the Central Secretariat has the same status as the off

9、icial versions. CENELEC members are the national electrotechnical committees of Austria, Belgium, Bulgaria, Croatia, Cyprus, the Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, the Netherlands, Norway, Poland

10、, Portugal, Romania, Slovakia, Slovenia, Spain, Sweden, Switzerland and the United Kingdom. BS EN 62418:2010EN 62418:2010 - 2 - Foreword The text of document 47/2043/FDIS, future edition 1 of IEC 62418, prepared by IEC TC 47, Semiconductor devices, was submitted to the IEC-CENELEC parallel vote and

11、was approved by CENELEC as EN 62418 on 2010-07-01. Attention is drawn to the possibility that some of the elements of this document may be the subject of patent rights. CEN and CENELEC shall not be held responsible for identifying any or all such patent rights. The following dates were fixed: latest

12、 date by which the EN has to be implemented at national level by publication of an identical national standard or by endorsement (dop) 2011-04-01 latest date by which the national standards conflicting with the EN have to be withdrawn (dow) 2013-07-01 _ Endorsement notice The text of the Internation

13、al Standard IEC 62418:2010 was approved by CENELEC as a European Standard without any modification. _ BS EN 62418:2010 2 62418 IEC:2010 CONTENTS 1 Scope.5 2 Test equipment.5 3 Test structure .5 3.1 Test structure patterns 5 3.2 Line pattern.5 3.3 Via chain pattern .5 3.3.1 Pattern types .5 3.3.2 Pat

14、tern for aluminium (Al) process.5 3.3.3 Pattern for copper (Cu) process.6 4 Stress temperature.6 5 Procedure 6 5.1 Stress void evaluation methods .6 5.2 Resistance measurement method6 5.3 Inspection method .7 6 Failure criteria 8 6.1 Resistance method8 6.2 Inspection method .8 7 Data interpretation

15、and lifetime extrapolation (resistance change method)8 8 Items to be specified and reported9 8.1 Resistance change method .9 8.2 Inspection method .10 Annex A (informative) Stress migration mechanism .11 Annex B (informative) Technology-dependent factors for aluminium 13 Annex C (informative) Techno

16、logy-dependent factors for copper .14 Annex D (informative) Precautions.15 Bibliography17 Figure A.1 Schematic representation of the stress-void formation mechanism in Al.11 Table 1 Void classification .7 BS EN 62418:201062418 IEC:2010 5 SEMICONDUCTOR DEVICES METALLIZATION STRESS VOID TEST 1 Scope T

17、his International Standard describes a method of metallization stress void test and associated criteria. It is applicable to aluminium (Al) or copper (Cu) metallization. This standard is applicable for reliability investigation and qualification of semiconductor process. 2 Test equipment A calibrate

18、d hot chuck or thermal chamber is required to subject the wafers or packaged test structures to the specified temperature (5 C) for the specified time. For resistance measurements dedicated equipment is needed. For void inspection deprocessing equipment is required to remove the scratch protection l

19、ayer. The inspections are performed with a scanning electron microscope (SEM). 3 Test structure 3.1 Test structure patterns Test structures shall be used for all metal layers which have to be inspected and several different types of structure may be used. The following two types of test structures a

20、re applicable for this test standard. NOTE For metallization without refractory shunt layers reflective notching at steps can occur in test structures with underlying topography, which will therefore tend to indicate a relatively worse stress-voiding behaviour. 3.2 Line pattern Parallel lines which

21、are patterned at the minimum linewidth allowed by design form an appropriate test structure. Unless otherwise specified a minimum length of 500 m and a total length of 1 cm to 1 000 cm are recommended condition. Single long isolated lines are recommended because stress voiding is often sensitive to

22、line-to-line separation. NOTE 1 Narrow lines are susceptible for stress voiding because the stress in the metal is typically higher in narrower lines than in wider lines. NOTE 2 The line length should be sufficient to insure that void nucleation sites will exist. 3.3 Via chain pattern 3.3.1 Pattern

23、types A via chain pattern is applicable as a test structure. For technology investigations a Kelvin-pattern for four-point measurements may also be used. 3.3.2 Pattern for aluminium (Al) process Via chains need to consist of a pattern of vias connected by minimum linewidth. The recommended number of

24、 vias is between 1 000 and 100 000. It is recommended to use isolated and long minimum linewidths. BS EN 62418:2010 6 62418 IEC:2010 3.3.3 Pattern for copper (Cu) process For Cu metallization the following structures are applicable: a) via chains with top and bottom metal segments with minimum allow

25、ed width; b) via chains with either the top or the bottom metal segment at minimum allowed width, and the other segment at the maximum width allowed for a single via; c) vias chains with both top and bottom metal segments at the maximum width allowed for a single via; d) Kelvin via structures, with

26、various widths for top and bottom metal. Chains with 1 000 100 000 vias are recommended. 4 Stress temperature To evaluate the impact of stress voiding on chip reliability under use conditions, accelerated testing is needed to generate voiding. The acceleration factor can be strongly affected by the

27、factors listed in Annex B and Annex C. Therefore, it is recommended to determine empirically the temperature range for accelerated testing which will maximize voiding. Recommended temperature ranges are given in 5.2 and 5.3. 5 Procedure 5.1 Stress void evaluation methods Two methods are specified fo

28、r the metallization stress void test: a resistance measurement method and a visual inspection method. The resistance measure method is the default method. The inspection method is applicable for use as a verification when no stress voiding is expected. It cannot be used for lifetime extrapolations.

29、This method is not applicable to Cu metallization. The inspection method shall not be used in case the visibility of voids is insufficient (see Note 2.) NOTE 1 The test method most likely to detect sensitivity to stress voiding and the one most usually conducted is constant temperature (isothermal)

30、aging, i.e., annealing or baking at temperatures between the passivation deposition temperature and the intended use temperature of the product. NOTE 2 This is the case for e.g. metallization with multiple metal levels, where the lower levels are not clearly visible, masking of voids by other proces

31、s features. 5.2 Resistance measurement method This method assumes the void growth and therefore resistance changes can be modelled, to obtain an acceleration factor for void growth 1, 21. Unless otherwise specified, the temperature condition shall be determined within the range of 150 C to 275 C. Sa

32、mples need to be separated into each temperature condition group and each group to be baked at the specified temperature. The procedure for resistance measurement is the following. a) Measure the resistance of the metal line or via chain. Resistance measurements shall be made at currents that minimi

33、ze joule heating. b) Bake the samples. Unless otherwise specified three temperatures are recommended to determine the parameters for the extrapolation model. When these parameters are known it is sufficient to test at a single temperature. In some cases, three temperatures may not be enough if the t

34、emperature range is not chosen correctly - there could be an inflection point in the activation energy versus temperature curve. If zero or very few failures are _ 1Figures in square brackets refer to the Bibliography. BS EN 62418:201062418 IEC:2010 7 observed it is not possible to determine an acti

35、vation energy, and a value can be selected from the literature. c) Measure the resistance. The samples may be cooled to room temperature for the resistance test. Cool in less than 2 h to room temperature. (Measurement of the resistance changes is, in principle, possible in situ at the aging temperat

36、ure.) Recommended read points: 168 h, 500 h, 1 000 h. NOTE Resistance measurements can extend beyond 2 000 h if saturation of void growth is desired. d) Calculate the relative change in resistance, as a percentage of the line-resistance prior to the bake, R (%). e) Calculate the failure rate (number

37、 of failed samples/total sample size). For failure criterion see Clause 6. f) Determine the total length of metal line inspected. g) If necessary, inspect failed samples to confirm the failure mode (see 5.3 for Al and e.g. 3 for Cu). 5.3 Inspection method The inspection method consists of the follow

38、ing steps. a) Bake the samples at a specified temperature for a specified time. The recommended temperature is 200 C for Al metallization. Recommended read points: 0 h, 168 h, 500 h, 1 000 h. Because the maximum void initiation and growth depends on the bake temperature, it is recommended to test at

39、 more than one temperature. The recommended temperature range is 150 C to 275 C for Al. Baking times can extend beyond 2 000 h if saturation of void growth is desired. b) Remove the scratch protection layer with standard deprocessing techniques. If a lower level of metallization needs to be inspecte

40、d, remove all other layers to expose the desired metallization level. NOTE Deprocessing for Al technologies can be done with e.g. RIE (reactive-ion etching) etch for plasma nitride/oxynitride/TEOS (incl. TiN), H2O2(50 C) for Ti/TiN barrier layers, and PES (Phosphoric Acid, Acetic Acid, Nitric Acid)

41、etch for Al. c) The sample shall not be sputtered with a carbon or gold layer prior to mounting in the Scanning Electron Microscope (SEM). d) Place the sample in the SEM, perpendicular to the incident electron beam. e) Adjust the magnification of the SEM, such that voids down to class A (see Table 1

42、) can be observed. Count the number of voids in the metal lines. Both wedge shaped voids and slit shaped voids shall be counted. f) Perform detailed inspection at an appropriate magnification of the voids observed, to classify these in accordance with Table 1. g) Determine the total length of metal

43、line inspected. h) Calculate the densities of Class A, Class B, and Class C voids NA, NB, NC(in voids per cm) with 60 % confidence using Poisson statistics. In order to classify the severity of the voids observed, the following classification scheme is used: Table 1 Void classification Class Void si

44、ze/linewidth Not counted A B C 10 % 10 %, , 25 % 25 %, , 50 % 50 % BS EN 62418:2010 8 62418 IEC:2010 6 Failure criteria 6.1 Resistance method The failure criterion for layered metallization with refractory shunt layers is a preselected percent resistance increase. The value shall be selected within

45、the range from 5 % to 30 %. NOTE If the metallization is a single-alloy component, such as AlSi or AlCu, the failure criterion of the method is an open-circuit of the test structure. 6.2 Inspection method The failure criterion is predefined maximum number of voids in the classes A, B, C, e.g. NC 1/c

46、m. 7 Data interpretation and lifetime extrapolation (resistance change method) The most straightforward way to interpret the data employs the median time to failure, where failure is determined by either a specified resistance shift or an open circuit. Because extended duration can be required to pr

47、oduce sizeable resistance shifts, a lower relative resistance failure criterion may be desired. A good way to avoid long test durations is to combine several test structures to effectively form one long line (or via chain) and plot the resistance change versus time. A well-behaved plot is usually ob

48、tained, which can be easily extrapolated to longer test times to determine the median time to failure. The time-to-failure for the chosen fractional change in resistance is found either from plots of the fractional resistance change versus stress time or the square root of stress time. Void growth i

49、s generally agreed to be a diffusive process and the increase in line resistance (for layered metallizations) is proportional to the void length, which shall be proportional to a diffusion length (the average distance a species (i.e. a vacancy in stress voiding mechanism) travels due to diffusion within the lifetime of the species). Thus a plot of fractional resistance change versus the square root of the time has the advantage of being approximately linear until voi