BS ISO 18257-2016 Space systems Semiconductor integrated circuits for space applications Design requirements《航天系统 航天应用的半导体集成电路 设计要求》.pdf

1、BS ISO 18257:2016Space systems Semiconductor integratedcircuits for space applications Design requirementsBSI Standards PublicationWB11885_BSI_StandardCovs_2013_AW.indd 1 15/05/2013 15:06BS ISO 18257:2016 BRITISH STANDARDNational forewordThis British Standard is the UK implementation of ISO 18257:20

2、16.The UK participation in its preparation was entrusted to Technical Committee ACE/68, Space systems and operations.A list of organizations represented on this committee can be obtained on request to its secretary.This publication does not purport to include all the necessary provisions of a contra

3、ct. Users are responsible for its correct application. The British Standards Institution 2016.Published by BSI Standards Limited 2016ISBN 978 0 580 87096 5 ICS 49.140 Compliance with a British Standard cannot confer immunity from legal obligations.This British Standard was published under the author

4、ity of the Standards Policy and Strategy Committee on 30 November 2016.Amendments/corrigenda issued since publicationDate T e x t a f f e c t e dBS ISO 18257:2016 ISO 2016Space systems Semiconductor integrated circuits for space applications Design requirementsSystmes spatiaux Circuits intgrs semi-c

5、onducteurs dapplications spatiales Exigences de conceptionINTERNATIONAL STANDARDISO18257First edition2016-11-15Reference numberISO 18257:2016(E)BS ISO 18257:2016ISO 18257:2016(E)ii ISO 2016 All rights reservedCOPYRIGHT PROTECTED DOCUMENT ISO 2016, Published in SwitzerlandAll rights reserved. Unless

6、otherwise specified, no part of this publication may be reproduced or utilized otherwise in any form or by any means, electronic or mechanical, including photocopying, or posting on the internet or an intranet, without prior written permission. Permission can be requested from either ISO at the addr

7、ess below or ISOs member body in the country of the requester.ISO copyright officeCh. de Blandonnet 8 CP 401CH-1214 Vernier, Geneva, SwitzerlandTel. +41 22 749 01 11Fax +41 22 749 09 47copyrightiso.orgwww.iso.orgBS ISO 18257:2016ISO 18257:2016(E)Foreword ivIntroduction v1 Scope . 12 Normative refere

8、nces 13 Terms and definitions 14 Abbreviated terms 25 General requirements . 26 Design process 36.1 Overview 36.2 Design input 56.3 Design phases and tasks . 66.3.1 Architecture design . 66.3.2 Logic design and circuit design . 76.3.3 Layout design 86.4 Mask making, package and testing . 107 Detaile

9、d requirements 107.1 Architectural design requirements 107.2 Logic design and circuit design requirements 107.3 Layout design requirements 117.4 Package design requirements . 117.4.1 Package structure design requirements .117.4.2 Packaging technology design requirements .127.4.3 Packaging electrical

10、 simulation analysis requirements 127.4.4 Packaging thermal simulation analysis .127.5 Reliability design requirements 127.5.1 Overview 127.5.2 Reliability design requirements 137.5.3 Antistatic design requirements 137.5.4 Low-power design requirements .137.5.5 Parameter modification and design marg

11、in optimization requirements 147.5.6 Electromagnetic compatibility design requirements 147.5.7 Radiation-hardened design requirements .147.6 Testability design requirements . 15Annex A (normative) Datasheet .16Annex B (informative) Guidance 17Bibliography .24 ISO 2016 All rights reserved iiiContents

12、 PageBS ISO 18257:2016ISO 18257:2016(E)ForewordISO (the International Organization for Standardization) is a worldwide federation of national standards bodies (ISO member bodies). The work of preparing International Standards is normally carried out through ISO technical committees. Each member body

13、 interested in a subject for which a technical committee has been established has the right to be represented on that committee. International organizations, governmental and non-governmental, in liaison with ISO, also take part in the work. ISO collaborates closely with the International Electrotec

14、hnical Commission (IEC) on all matters of electrotechnical standardization.The procedures used to develop this document and those intended for its further maintenance are described in the ISO/IEC Directives, Part 1. In particular, the different approval criteria needed for the different types of ISO

15、 documents should be noted. This document was drafted in accordance with the editorial rules of the ISO/IEC Directives, Part 2 (see www.iso.org/directives).Attention is drawn to the possibility that some of the elements of this document may be the subject of patent rights. ISO shall not be held resp

16、onsible for identifying any or all such patent rights. Details of any patent rights identified during the development of the document will be in the Introduction and/or on the ISO list of patent declarations received (see www.iso.org/patents).Any trade name used in this document is information given

17、 for the convenience of users and does not constitute an endorsement.For an explanation on the meaning of ISO specific terms and expressions related to conformity assessment, as well as information about ISOs adherence to the World Trade Organization (WTO) principles in the Technical Barriers to Tra

18、de (TBT) see the following URL: www.iso.org/iso/foreword.html.The committee responsible for this document is ISO/TC 20, Aircraft and space vehicles, Subcommittee SC 14, Space systems and operations.iv ISO 2016 All rights reservedBS ISO 18257:2016ISO 18257:2016(E)IntroductionNormative design requirem

19、ents of semiconductor integrated circuits for space applications largely determine the reliability of an integrated circuit (IC) and its adaptability to space environment, thereby affecting the reliability of space systems. IC tests and experiments based on product specification only can provide a c

20、omprehensive evaluation of its reliability. Once applied to space systems, the design flaws will directly affect the implementation of aerospace engineering. The development of design requirements for semiconductor ICs for space applications can ensure its reliability and space suitability from its

21、very source to meet the space application requirements. ISO 2016 All rights reserved vBS ISO 18257:2016BS ISO 18257:2016Space systems Semiconductor integrated circuits for space applications Design requirements1 ScopeThis document specifies the basic design requirements for semiconductor ICs for spa

22、ce applications, including its design process, as well as required tasks and requirements of each stage. Requirements of specific circuit design are not included.2 Normative referencesThe following documents are referred to in text in such a way that some or all of their content constitutes requirem

23、ents of this document. For dated references, only the edition cited applies. For undated references, the latest edition of the referenced document (including any amendments) applies.IEC 61967-2, Integrated circuits Measurement of electromagnetic emissionsIEC 62132, Integrated circuits Measurement of

24、 electromagnetic immunityIEC 62215-3:2013, Integrated circuits Measurement of impulse immunity Part 3: Non-synchronous transient injection methodIEEE 1149.1, IEEE standard for test access port and boundary Scan architecture3 Terms and definitions For the purposes of this document, the terms defined

25、in ISO 10795 and the following apply.ISO and IEC maintain terminological databases for use in standardization at the following addresses: IEC Electropedia: available at http:/www.electropedia.org/ ISO Online browsing platform: available at http:/www.iso.org/obp3.1programmable logic devicePLDhardware

26、-programmable deviceEXAMPLE FPGA, CPLD, etc.3.2suitabilitydegree to which a product meets its requirements3.3environment adaptabilityability to achieve the entire products intended functions, performance and (or) capacity for protecting itself under various environments within its life cycle3.4testa

27、bilityability to perform function and performance testing of the circuit, position the failure of the circuit and select qualified circuit chip as soon as possibleINTERNATIONAL STANDARD ISO 18257:2016(E) ISO 2016 All rights reserved 1BS ISO 18257:2016ISO 18257:2016(E)4 Abbreviated termsASIC applicat

28、ion specific integrated circuitBIST built-in self testCMOS complementary metal oxide semiconductorDFT design for testDRC design rule checkingEMC electro-magnetic compatibilityERC electrical rule checkingESD electrostatic dischargeFPGA field programmable gate arrayIC integrated circuitI/O input/outpu

29、tIP intellectual propertyJFET junction field effect transistorMOSFET metallic oxide semiconductor field effect transistorNMOS N-channel metal oxide semiconductorRAM random access memoryRC resistance capacitanceROM read only memoryRTL register transfer levelSAR ADC successive approximation register a

30、nalogue digital converterSCR silicon controlled rectifierSEL single event latch-upSET single event transientSEU single event upsetSOI silicon on insulatorSOS silicon on sapphire5 General requirementsGeneral requirements in designing semiconductor ICs for space applications include:a) process conduct

31、ed under a fault-tolerant system with design requirements;NOTE 1 Special implements are allowed for different types of ICs for space applications.2 ISO 2016 All rights reservedBS ISO 18257:2016ISO 18257:2016(E)b) adherence to existing standards and regulations during the design process;c) feasibilit

32、y and risk analysis of requirements from aerospace customer to validate the rationality of its functional and performance requirements;d) conversion of users requirements into design input, which may involve the following steps:1) derating the design criteria;NOTE 2 Derate on the basis of nominal st

33、ress according to the stress of the circuit. The key is the level and effects. Derating can improve reliability, but takes into consideration issues such as reliability, size, weight and cost.2) applying fault-tolerant design and adopting rational use of redundant technology;3) ensuring the characte

34、ristics of the orbit thermal environment for reliable thermal design;4) considering radiation hardness to ensure grade requirements, if necessary;5) taking note of the life of customers requirements (mean time to failure);e) decomposition of the design input requirements to each design stage accordi

35、ng to its tasks.NOTE 3 Implement and validate each step until all objectives and requirements of a semiconductor IC for space applications are achieved.6 Design process6.1 OverviewIC designs generally include architecture design, logic design, circuit design and layout design. In order to ensure the

36、 validity of the design, computer simulation and verification of its results at each stage are necessary. Figure 1 illustrates the IC design flow. ISO 2016 All rights reserved 3BS ISO 18257:2016ISO 18257:2016(E)Figure 1 Integrated circuit design flow diagramIn designing semiconductor ICs for space a

37、pplications, designers have to follow a general IC design process to convert users general and special requirements (i.e. user-oriented features, performance and reliability requirements, etc.) into design input, thereby accomplishing the design goals of each stage to meet the overall requirements.

38、Figure 2 illustrates the decomposition of tasks in the design process of semiconductor IC for space applications.4 ISO 2016 All rights reservedBS ISO 18257:2016ISO 18257:2016(E)Figure 2 Decomposition of tasks in designing semiconductor IC for space applications6.2 Design inputA design input document

39、 will be formed after completing the requirements definition. Design input generally includes (modifications are allowed according to specific circuit requirements) the following:a) system division, system configuration and operating mode;b) system interface, external device communication protocols,

40、 including memory-mapped register;c) operating frequency range;d) constraints of electrical parameter;e) functional requirements; ISO 2016 All rights reserved 5BS ISO 18257:2016ISO 18257:2016(E)f) application algorithm;g) reset and power dissipation requirements;h) error handling;i) testing mode;j)

41、fault coverage requirements of digital circuit testing;k) key signal timing;l) constraints of the normal working environment;m) constraints of the special space working environment, which includes1) space radiation,2) heat dissipation in vacuum, and3) in-space charging effects (i.e. ESD, latch-up);n

42、) power dissipation budget;o) physical and mechanical constraints include: pin distribution, size, packaging;p) reusability and additional features of the product;q) new technologies;r) intellectual property of design;s) IP cores that are necessary and with verification.6.3 Design phases and tasks6.

43、3.1 Architecture design6.3.1.1 OverviewFinding an architecture design that offers efficient functionality at minimal cost, while meeting users objectives and constraints, is important.6.3.1.2 Design contentThe following is the architecture design process.a) Define the chip architecture, verify and r

44、ecord the completion of functions of the basic module, as well as interfaces and interactions.b) Select and validate the chip architecture.c) Ensure that all definitions and selections are in accordance with the documents made in the definition phase.d) Ensure that the output includes:1) a simulatio

45、n model,2) the results verification, and3) a preliminary datasheet.6 ISO 2016 All rights reservedBS ISO 18257:2016ISO 18257:2016(E)The datasheet shall conform to the requirements of Annex A.Verification: For example, complex digital circuit research and development will be realized through FPGA samp

46、le or tested by simulation; digital circuit code coverage requirements; requirements for hardware and software interaction; applications of the code rules.6.3.1.3 Design verificationThe following is the architectural design verification process.a) Verify whether the defined architecture meets demand

47、s through appropriate simulation and analysis techniques.b) Complete independent verification.c) Finish the primary placement and routing after the hardware unit is connected, making sure each unit is placed effectively under the given constraints.NOTE Does not apply to PLD design.d) Put in place a

48、back-up plan, in case conflicts occur (i.e. power dissipation and speed, performance, pin number and package size, complexity and area).e) Establish a final system design.f) Complete the initial datasheet.6.3.2 Logic design and circuit design6.3.2.1 OverviewIn this stage, the high-level system desig

49、n is transmitted and transformed to unit-level architecture description with the chosen technology library, and the input information of the next phase, such as layout constraints, placement and routing, and product testing and detailed pin description, etc. are generated. Logic design and circuit design are included. For digital circuits, verified gate-level netlist is generated; while for analogue circuit, verified transistor-level netlist is generated.6.3.2.2 Design contentThe following is the logic des