CAN CSA-ISO IEC 13961-2002 Information technology – Scalable Coherent Interface (SCI).pdf

1、 Information technology Scalable Coherent Interface (SCI)Reference numberISO/IEC 13961:2000(E)IEEE Std 1596, 1998 EditionNational Standard of CanadaCAN/CSA-ISO/IEC 13961:02(ISO/IEC 13961:2000 / IEEE Std 1596, 1998)International Standard ISO/IEC 13961:2000 / IEEE Std 1596, 1998 (first edition, 2000-0

2、7) has beenadopted without modification (IDT) as CSA Standard CAN/CSA-ISO/IEC 13961:02, which has been approvedas a National Standard of Canada by the Standards Council of Canada.ISBN 1-55324-987-9 December 2002The Canadian Standards Association (CSA), The Standards Council of Canada is theunder who

3、se auspices this National Standard has been coordinating body of the National Standards system, produced, was chartered in 1919 and accredited by a federation of independent, autonomousthe Standards Council of Canada to the National organizations working towards the furtherStandards system in 1973.

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16、SA services, write toCanadian Standards Association5060 Spectrum Way, Suite 100Mississauga, Ontario, L4W 5N6CanadaAlthough the intended primary application of this Standard is stated in its Scope, it is importantto note that it remains the responsibility of the users to judge its suitability for the

17、ir particular purpose.Registered trade-mark of Canadian Standards AssociationCAN/CSA-ISO/IEC 13961:02 Information technology Scalable Coherent Interface (SCI)December 2002 Canadian Standards Association CSA/1CAN/CSA-ISO/IEC 13961:02Information technology ScalableCoherent Interface (SCI)CSA PrefaceSt

18、andards development within the Information Technology sector is harmonized with internationalstandards development. Through the CSA Technical Committee on Information Technology (TCIT),Canadians serve as the Canadian Advisory Committee (CAC) on ISO/IEC Joint Technical Committee 1 onInformation Techn

19、ology (ISO/IEC JTC1) for the Standards Council of Canada (SCC), the ISO memberbody for Canada and sponsor of the Canadian National Committee of the IEC. Also, as a member of theInternational Telecommunication Union (ITU), Canada participates in the International Telegraph andTelephone Consultative C

20、ommittee (ITU-T).This International Standard was reviewed by the CSA TCIT under the jurisdiction of the StrategicSteering Committee on Information Technology and deemed acceptable for use in Canada. (Acommittee membership list is available on request from the CSA Project Manager.) From time to time,

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22、bythe Technical Committee and has been approved as a National Standard of Canada by the StandardsCouncil of Canada.December 2002 Canadian Standards Association 2002All rights reserved. No part of this publication may be reproduced in any form whatsoever without the priorpermission of the publisher.

23、ISO/IEC material is reprinted with permission. Where the words “thisInternational Standard” appear in the text, they should be interpreted as “this National Standard ofCanada”. Inquiries regarding this National Standard of Canada should be addressed to Canadian Standards Association 5060 Spectrum Wa

24、y, Suite 100, Mississauga, Ontario, Canada L4W 5N6 1-800-463-6727 416-747-4044www.csa.caINTERNATIONALSTANDARDISO/IEC13961IEEEStd 1596First edition2000-07Information technology Scalable Coherent Interface (SCI)Reference numberISO/IEC 13961:2000(E)IEEE Std 1596, 1998 EditionAbstract: The scalable cohe

25、rent interface (SCI) provides computer-bus-like services but,instead of a bus, uses a collection of fast point-to-point unidirectional links to provide the farhigher throughput needed for high-performance multiprocessor systems. SCI supportsdistributed, shared memory with optional cache coherence fo

26、r tightly coupled systems, andmessage-passing for loosely coupled systems. Initial SCI links are defined at 1 Gbyte/s (16-bitparallel) and 1 Gb/s (serial). For applications requiring modular packaging, an interchangeablemodule is specified along with connector and power. The packets and protocols th

27、at implementtransactions are defined and their formal specification is provided in the form of computerprograms. In addition to the usual read-and-write transactions, SCI supports efficientmultiprocessor lock transactions. The distributed cache-coherence protocols are efficient andcan recover from a

28、n arbitrary number of transmission failures. SCI protocols ensure forwardprogress despite multiprocessor conflicts (no deadlocks or starvation).Keywords: bus architecture, bus standard, cache coherence, distributed memory, fiber optic,interconnect, I/O system, link, mesh, multiprocessor, network, pa

29、cket protocol, ring, seamlessdistributed computer, shared memory, switch, transaction set.The Institute of Electrical and Electronics Engineers, Inc.345 East 47th Street, New York, NY 10017-2394, USACopyright 1998 by the Institute of Electrical and Electronics Engineers, Inc.All rights reserved. Fir

30、st published in 1998.ISBN 2-8318-5375-3No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, withoutthe prior written permission of the publisher.INTERNATIONALSTANDARDISO/IEC13961IEEEStd 1596First edition2000-07Information technology Scalable Cohe

31、rent Interface (SCI)SponsorMicroprocessor and Microcomputer Standards Subcommitteeof the IEEE Computer SocietyPRICE CODEXFFor price, see current catalogue 2 ISO/IEC 13961:2000(E)IEEE Std 1596, 1998 EditionCopyright 1998 IEEE. All rights reserved.CONTENTSPageFOREWORD 12Clause1 Introduction 191.1 Docu

32、ment structure. 191.2 SCI overview 201.2.1 Scope and directions. 201.2.2 The SCI approach. 211.2.3 System configurations. 221.2.4 Initial physical models. 231.2.5 SCI node model 241.2.6 Architectural parameters . 251.2.7 A common CSR architecture . 251.2.8 Structure of the specification. 261.3 Inter

33、connect topologies. 261.3.1 Bridged systems . 261.3.2 Scalable systems 271.3.3 Interconnected systems 271.3.4 Backplane rings 271.3.5 Interconnected rings . 281.3.6 Rectangular grid interconnects 291.3.7 Butterfly switches 301.3.8 Vendor-dependent switches 311.4 Transactions. 311.4.1 Packet formats

34、321.4.2 Input and output queues . 331.4.3 Request and response queues 341.4.4 Switch queues. 361.4.5 Subactions 361.4.6 Remote transactions (through agents). 391.4.7 Move transactions. 411.4.8 Broadcast moves 421.4.9 Broadcast passing by agents 431.4.10 Transaction types 441.4.11 Message passing 451

35、.4.12 Global clocks 451.4.13 Allocation protocols. 461.4.14 Queue allocation. 471.5 Cache coherence 491.5.1 Interconnect constraints 491.5.2 Distributed directories . 491.5.3 Standard optimizations 501.5.4 Future extensions . 501.5.5 TLB purges . 53ISO/IEC 13961:2000(E) 3 IEEE Std 1596, 1998 Edition

36、Copyright 1998 IEEE. All rights reserved.Clause Page1.6 Reliability, availability, and support (RAS). 541.6.1 RAS overview . 541.6.2 Autoconfiguration 541.6.3 Control and status registers 541.6.4 Transmission-error detection and isolation 551.6.5 Error containment . 551.6.6 Hardware fault retry (rin

37、glet-local, physical layer option) . 561.6.7 Software fault recovery (end-to-end) . 561.6.8 System debugging 571.6.9 Alternate routing . 571.6.10 Online replacement. 572 References, glossary, and notation 582.1 Normative references 582.2 Conformance levels 582.3 Terms and definitions . 592.4 Bit and

38、 byte ordering. 662.5 Numerical values 682.6 C code 683 Logical protocols and formats 683.1 Packet formats 683.1.1 Packet types . 683.2 Send and echo packet formats 693.2.1 Request-send packet format . 693.2.2 Request-echo packet format . 723.2.3 Response-send packet 743.2.4 Standard status codes 76

39、3.2.5 Response-echo packet format. 783.2.6 Interconnect-affected fields. 793.2.7 Init packets . 803.2.8 Cyclic redundancy code (CRC) . 813.2.9 Parallel 16-bit CRC calculations 823.2.10 CRC stomping. 843.2.11 Idle symbols 853.3 Logical packet encodings 863.3.1 Flag coding . 863.4 Transaction types .

40、893.4.1 Transaction commands . 893.4.2 Lock subcommands 923.4.3 Unaligned DMA transfers 943.4.4 Aligned block-transfer hints. 953.4.5 Move transactions. 973.4.6 Global time synchronization 983.5 Elastic buffers. 993.5.1 Elasticity models . 993.5.2 Idle-symbol insertions . 1003.5.3 Idle-symbol deleti

41、ons 101 4 ISO/IEC 13961:2000(E)IEEE Std 1596, 1998 EditionCopyright 1998 IEEE. All rights reserved.Clause Page3.6 Bandwidth allocation. 1013.6.1 Fair bandwidth allocation 1023.6.2 Setting ringlet priority 1043.6.3 Bandwidth partitioning. 1063.6.4 Types of transmission protocols 1083.6.5 Pass-transmi

42、ssion protocol . 1083.6.6 Low-transmission protocol. 1113.6.7 Idle insertions . 1143.6.8 High-transmission protocol 1143.7 Queue allocation. 1163.7.1 Queue reservations. 1163.7.2 Multiple active sends. 1183.7.3 Unfair reservations 1193.7.4 Queue-selection protocols. 1193.7.5 Re-send priorities 1193.

43、8 Transaction errors. 1203.8.1 Requester timeouts (response-expected packets) . 1203.8.2 Time-of-death timeout (optional, all nodes) . 1203.8.3 Responder-processing errors 1223.9 Transmission errors 1233.9.1 Error isolation . 1233.9.2 Scrubber maintenance 1253.9.3 Producer-detected errors 1263.9.4 C

44、onsumer-detected errors. 1283.10 Address initialization. 1293.10.1 Transaction addressing. 1293.10.2 Reset types. 1313.10.3 Unique node identifiers . 1323.10.4 Ringlet initialization. 1333.10.5 Simple-subset ringlet resets 1353.10.6 Ringlet resets 1353.10.7 Ringlet clears (optional) 1373.10.8 Insert

45、ing initialization packets . 1383.10.9 Address initialization . 1393.11 Packet encoding . 1403.11.1 Common encoding features (L18) . 1403.11.2 Parallel encoding with 18 signals (P18). 1413.11.3 Serial encoding with 20-bit symbols (S20). 1413.12 SCI-specific control and status registers . 1443.12.1 S

46、CI transaction sets 1443.12.2 SCI resets. 1453.12.3 SCI-dependent fields within standard CSRs 1453.12.4 SCI-dependent CSRs 1483.12.5 SCI-dependent ROM. 1513.12.6 Interrupt register formats. 1553.12.7 Interleaved logical addressing. 157ISO/IEC 13961:2000(E) 5 IEEE Std 1596, 1998 EditionCopyright 1998

47、 IEEE. All rights reserved.Clause Page4 Cache-coherence protocols 1584.1 Introduction. 1584.1.1 Objectives. 1584.1.2 SCI transaction components . 1584.1.3 Physical addressing 1594.1.4 Coherence directory overview . 1594.1.5 Memory and cache tags 1604.1.6 Instruction-execution model 1614.1.7 Coherenc

48、e document structure . 1624.2 Coherence update sequences. 1634.2.1 List prepend 1634.2.2 List-entry deletion . 1654.2.3 Update actions 1674.2.4 Cache-line locks . 1674.2.5 Stable sharing lists 1684.3 Minimal-set coherence protocols. 1714.3.1 Sharing-list updates 1714.3.2 Cache fetching 1714.3.3 Cach

49、e rollouts. 1734.3.4 Instruction-execution model 1744.4 Typical-set coherence protocols 1754.4.1 Sharing-list updates 1754.4.2 Read-only fetch. 1754.4.3 Read-write fetch 1774.4.4 Data modifications 1784.4.5 Mid and head deletions . 1794.4.6 DMA reads and writes. 1814.4.7 Instruction-execution model 1834.5 Full-set coherence protocols . 1844.5.1 Full-set option summary 1844.5.2 CLEAN-list creation. 1844.5.3 Sharing-list additions 1854.5.4 Cache washing . 1874.5.5 Cache flushing 1894.5.6 Cache cleansing . 1914.5.7 Pairwise sharing . 1924.5.