1、CEPT T/CD*Ol-OS*E 232bY1Y 0003071 Y Page E 1 Recommendation T/CD O1 -05 E (Ostende 1979, revised at Cannes 1983) concerning the engineering requirements for a 2,400/4,800 bit/s modem for use on telephone type circuits Recommendation proposed by Working Group T/WG 1 O “Data Communications” (CD) Text
2、of the revised Recommendation adopted by the “Telecommunications” Commission “The Conference of European Post and Telecommunications Administrations, Considering - that Recommendation T/CD 01-01 contains the text of the Specifications of the general engineering requirements - that working group CD h
3、as studied under the auspices of question CD 1 the harmonization of voice band modems for data circuit terminating equipment for analogue and digital networks; for 4,800/2,400 bit/s. Recommends - that the attached Specification of engineering requirements for a 4,800/2,400 bit/s modem for use on the
4、 public telephone network as contained in Annex 1 to this Recommendation should be taken into account by all CEPT Administrations when implementation of such a piece of equipment is being planned by Administrations. Administrations are free to stipulate additional requirements, and also which of the
5、 optional requirements, if any, are to be provided. Note 1; It should be noted that this specification is subjected of continuing study and possible amendment. Note 2: The Annex is an integral part of the Recommendation. Note 3: Bars at the left hand margin indicate that the wording of this specific
6、ation is identical with CCITT Recommendation V.27ter for the relevant item. a a a Edition of November 30, 1985 CEPT T/CD*OL-OSUE D 2326434 0003072 b D Annex 1 . Contents Section A . Common requirements . 1 . General . 2 . Data signalling rate 3 . Interfaces 4 . Modulation and coding . 5 . Scrambler
7、6 . Line signal level 7 . Threshold of data channel received line signal detector . 8 . Performance requirements . Section B . Network dependent requirements No specific requirements . Section C . Optional requirements 1 . Modem for use on telephone network . 2 . Backword channel . 3 . Echo suppress
8、or . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T/CD O1 -05 E Page 3 5 5 5 5 6 8 9 9 9 10 10 10 11 Edition of November 30. 1985 CEPT T/CD*OL-OS*E 79 2326434 0003073 H T/CD O1 -05 E Page 5 Section A. Basic requirements 1. 2. 3. 3.1. 3.2. 3.3. 3.4. 3.
9、4.1. 3.4.2. GENERAL The modem must meet the following items and must comply to CCITT Recommendation V.27ter and V.241V.28. The modem is intended to be used over switched public telephone network. The principal characteristics for this recommended modem at 4,800/2,400 bit/s are as follows : (a) opera
10、tes in a haif-duplex mode on the general switched telephone network, with or without protection against talker echo; (b) inclusion of an automatic adaptive equalizer. The modem must comply, with the removal of optional plug-in unit, to the CCITT Recommendation V.27bis and operate in full-duplex or h
11、aif-duplex mode over 4 wire leased circuits or in half-duplex mode over 2 wire leased circuits. The modem is intended to be used over any general leased circuits not necessarily conforming to Recom- mendation M.1020. A provision for a fast start-up sequence is made to allow the use of this modem for
12、 multipoint polling application if the circuits used conform to Recommendation M. 1020. With the insertion of optional plug-in units, the modem may have: (a) a backward channel at modulation rate up to 75 baud. DATA SIGNALLING RATE The data signalling rate shall be 4,800 bit/s +0.01%, with 8-phase d
13、ifferentially encoded modulation. The modulation rate is 1,600 baud. The reduced data signalling rate shall be 2,400 bit/s or, - circuit 107 (where circuit 105 is already ON) to the appearance of the corresponding ON or OFF condition on circuit 106. r Edition of November 30, 1985 -c_c CEPT T/CD*Ol-O
14、S*E 2326434 0003074 T T/CD O1 -05 E Page 6 3.4.3. 4. 4.1. I I 4.1.1. 4.1.2. I 4.2. 4.2.1. 4.3. 4.3.1. 4.4. 4.4.1. 4.4.2. Clamping in half-duplex mode The modem, when operating in half-duplex mode on a two-wire line, shall hold, whereimplemented, circuit 104 in the binary 1 condition and circuit 109
15、in the OFF condition when circuit 105 is in the ON condition and, where required to protect circuit 104 from false signals, for a period of 150f25 ms following the ON to OFF transition on circuit 105. The use of this additional delay is optional based on system considerations. MODULATION AND CODING
16、Carrier frequency The carrier frequency is to be 1,800k 1 Hz. No separate pilote tones are provided. Spectrum at 4,800 bitls A 50% raised cosine energy spectrum shaping is equally divided between the receiver and transmitter. The energy density spectrum, respect to the maximum energy density between
17、 1,000 Hz and 2,600 Hz, should not exceed the limits specified in Figure 1. The transmitter energy spectrum shall be shaped in such a way that when continuous data ONEs are applied to the input of the scrambler, the resulting transmitted spectrum shall have a substantially linear phase characteristi
18、c over the band of 1,100 Hz to 2,500 Hz and inside the limits specified in Figure 2. Spectrum at 2,400 bitls A minimum of 50% raised cosine energy spectrum shaping is equally divided between the receiver and transmitter. The energy density spectrum, respect to the maximum energy density between 1,20
19、0 Hz and 2,400 Hz, should not exceed the limits specified in Figure 3. The transmitter energy spectrum shall be shaped in such a way that when continuous data ONEs are applied to the input of the scrambler, the resulting transmitted spectrum shall have a substantially linear phase characteristic ove
20、r the band of 1,300 to 2,300 Hz and inside the limits specified in Figure 4. Operation at 4,800 bit/s Encoding data bits The data stream to be transmitted is divided into groups of three consecutive bits (tribits). Each is encoded as a phase change relative to the phase of the preceding signal tribi
21、ts element (see Table 3). At the receiver, the tribits are decoded and the bits are reassembled in correct order. The left-hand digit of the tribit is the one occurring first in the data stream as it enters the modulator portion of the modem after the scrambler. Operation at 2,400 bit/s Encoding dat
22、a bits At 2,400 bit/s the data stream is divided into groups of two bits (dibits). Each dibit is encoded as a phase change relative to the phase of the immediately preceding signal element (see Table 4). At the receiver, the dibits are decoded and reassembled in correct order. The left-hand digit of
23、 the dibit is the one occurring first in the data stream as it enters the modulator portion of the modem after the scrambler. Operating sequences “Turn-on ” sequence During the interval between the OFF to ON transition of circuit 105 and the OFF to ON transition of circuit 106, synchronizing signals
24、 for proper conditioning of the receiving modem must be generated by the transmitting modem. These are signals to establish carrier detect, AGC if required, timing synchronization, equalizer convergence and descrambler synchronization. The synchronizing signals are defined in two separate sequences
25、with the long sequence used once at the beginning of the established connection and the short sequence used for subsequent turn-around in which the equalizer training pattern is used to update and refine equalizer convergence. Two sequences are defined, i.e., (a) a short one for turn-around operatio
26、n, (b) a longer one for initial establishment of connection. The sequence (b) is only used after the first OFF to ON transition of circuit 105 following the OFF to ON transition of circuit 107, or at the OFF to ON transition of circuit 107 if the circuit 105 is already ON. After every subsequent OFF
27、 to ON transition of circuit 105, the sequence (a) is used. The sequences for both data rates, are divided into five segments as in Table 5. The composition of segment 3 is continuous 180” phase reversals on line for 14 symbol intervals in the case of sequence (a), for 50 symbol intervals in the cas
28、e of sequence (b). Edition of November 30, 1985 I CEPT T/CD*OL-OS*E H 2326414 0003075 1 W 4.4.3. 4.4.3.1. 4.4.3.2. 4.4.4. 4.4.5. 4.4.6. 4.5. 4.6. 4.7. T/CD O1 -05 E Page 7 Segment 4 is composed of an equalizer conditioning pattern which is derived from a pseudo-random sequence generated by the polyn
29、omial : For operation at 4,800 bit/s and 2,400 bit/s the equalizer conditioning pattern is derived by using every third bit of the pseudo-random sequence defined in paragraph Section A 4.4.3. When the derived pattern contains a ZERO, O“ phase change is transmitted; when it contains a ONE, 180“ phase
30、 change is transmitted. Segment 4 begins with O“, 180“, 180“, 180“, 180“, 180“, O“, . according to the derived pattern and continues for 58 symbol intervals in the case of sequence (a) and for 1,074 symbol intervals in the case of sequence (b). An example of detailed sequence generation is described
31、 in the paragraph Section A 4.7. On leased circuits, considering that there exist modems which comply with paragraph Section A 4.4.3.1. at 4,800 bit/s, but which differ in their turn-around sequences at 2,400 bit/s, the following alternative equalizer conditioning patterns are defined (Section B): i
32、) in the first alternative, the equalizer conditioning pattern is identical to that defined in paragraph 4.4.3.1. (Note) ; ii) in the second alternative, the equalizer conditioning pattern is derived by using every second bit of the pseudo-random pattern defined in paragraph 4.4.3. When the derived
33、sequence contains a ZERO, O“ phase change is transmitted; when it contains a ONE, 180“ phase change is transmitted. Segment 4 begins with the sequence O“, 180“, O“, 180“, 180“, O“, 180“, . according to the derived pattern and continues for 58 symbol intervals in the case of sequence (a) and for 1,07
34、4 symbol intervals in the case of sequence (b). Segment 5 commences transmission according to the encoding described in 4.2. and 4.3. above with continuous data ONES applied to the input of the data scrambler. Segment 5 is 8 symbol intervals. At the end of segment 5, circuit 106 is turned ON and use
35、d data are applied to the input of the data scrambler. The phase change sequences for segments 4 and 5 for 4,800 bit/s and 2,400 bit/s are shown in Table 6. “Turn-of sequence The line signal emitted after the ON to OFF transition of circuit 105 is divided into two segments as in Table 7. If an OFF t
36、o ON transition of circuit 105 occurs during the turn-off sequence, it will not be taken into account until the end of the turn-off sequence. In addition, in the case of half-duplex operation on two-wires, if circuit 105 goes ON during the reception of the segment A of the TURN OFF sequence, optiona
37、lly the transmission of the TURN ON sequence shall be started within a time period of less than 20 ms after the end of reception of segment A. 1 +x-6+x-7 Received signal frequency tolerance Noting that the carrier frequency tolerance allowance of the transmitter is f 1 Hz and assuming a maximum drif
38、t of f6 Hz in the connection between the modems, then the receiver must be able to accept errors of at least f7 Hz in the received frequencies. Timing arrangement Clocks should be included in the modem to provide the data terminal equipment with transmitter element timing (Recommendation V.24, circu
39、it 114) and receiver signal element timing (Recommendation V.24, circuit 115). The transmitter element timing may be originated in the data terminal equipment and be transferred to the modem via the appropriate interchange circuit (Recommendation V.24, circuit 1 13). Equalizer An automatic adaptive
40、equalizer shall be provided in the receiver. The receiver shall incorporate a means of detecting loss of equalization and be able to recover equalization from the normal data modulated received line signal without initiating a new synchronizing signal from the distant transmitter. At 4,800 bit/s, ra
41、pid convergence for the equalizer with the least amount of circuitry is more readily accomplished by sending only an in-phase or out-of-phase carrier during training. This implies that the only tribits sent to the modulator will be O01 (0“ phase) or 111 (180“ phase). Refer to Figure 5 for circuitry
42、to generate the sequence and Figure 7 for timing the sequence. Let T1 be a timing signal equal to 1,600 Hz (symbol clock), that is true (high) for one 4,800 Hz period, and low for two 4,800 Hz clock periods. T2 is the inversion of T1. Nore: On switched circuits only the alternative i) must be used.
43、Edition of November 30, 1985 CEPT T/CD*OL-OS*E 2326434 0003076 3 TfCD 01-05 E Page 8 During T1 select the input to the scrambler, during T2 select the first stage of the scrambler. During the period when T2 is high, C forces the output high. This may be accomplished by circuitry shown in Figure 6. I
44、f T1 is forced continually high and T2 is forced continually low, normal operation is restored. In order to ensure consistent training, the same pattern should always be sent. To accomplish this the data input to the scrambler should be in mark hold during the training, and the first seven stages of
45、 the scrambler should be loaded with O O 1 1 1 1 O (right-hand-most first in time) on the first coincidence on T1 and the signal that will cause the mute should be removed form the transmitter output. (Generally this signal will be request to send.) This particular starting point was chosen in order
46、 to ensure a pattern that has continuous 180“ phase reversals at the beginning in order to ensure rapid clock acquisition, followed by a pattern that will ensure equalizer convergence. Within eight symbol intervals prior to the ON condition of ready for sending, the scrambler should be switched to n
47、ormal operation, keeping the scrambler in mark hold until RFS, to synchronize the de- scrambler. Note: At 2,400 bit/s, a similar technique may be used with appropriate clocking changes, as shown in Table 8. 5. 5.1. 5.2. 5.3. SCRAMBLER A self-synchronizing scrambler/descrambler having the generating
48、polynomial: with additional guards against repeating pattern of 1, 2, 3, 4, 6, 8, 9 and 12 bits, shall be included in the modem. Figure 6 shows a suitable logical arrangement. At the transmitter the scrambler shall effectively divide the message polynomial, of which the input data sequence represent
49、s the coefficients in descending order, by the scrambler generating polynomial to generate the transmitted sequence, and at the receiver the received polynomial, of which the received data sequence represents the coefficients in descending order, shall be multiplied by the scrambler generating polynomial to recover the message sequence. 1 +X4+X-7 Scrambling The message polynomial is divided by the generating polynomial (see Figure 5 and 8). The coefficients of the quotient of this division taken in descending order form the data sequence to be transmitted. The transmitted bit sequence
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