DLA CATS-2009 CAPACITORS FIXED ELECTROLYTIC (ALUMINUM OXIDE) (POLARIZED) NON-ESTABLISHED RELIABILITY AND ESTABLISHED RELIABILITY STYLES CU16 (UNINSULATED) CU17 (INSULATED) AND CUR1.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV REV STATUS OF PAGES PAGE 1 2 3 4 5 6 7 8 PMIC N/A PREPARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Phu H.

2、Nguyen APPROVED BY Charles F. Saffle TITLE MICROCIRCUIT, DIGITAL, CMOS HEX VOLTAGE LEVEL SHIFTER FOR TTL TO CMOS OR CMOS TO CMOS OPERATION, MONOLITHIC SILICON SIZE A CODE IDENT. NO. 16236 DWG NO. V62/09606 YY MM DD 09-02-04 REV PAGE 1 OF 8 AMSC N/A 5962-V027-09 Provided by IHSNot for ResaleNo reprod

3、uction or networking permitted without license from IHSDEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09606 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance CMOS hex voltage level shifter for TTL to CMOS or C

4、MOS to CMOS operation microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the e

5、ngineering documentation: V62/09606 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 CD4504B-EP CMOS hex voltage level shifter for TTL to CMOS or CMOS to CMOS operation 1.2.2 Case outline(s)

6、. The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 16 JEDEC MO-153 Plastic small outline package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Materia

7、l A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other 1.3 Absolute maximum ratings. DC supply voltage range, Voltage referenced to VSS terminal (VDD) . -0.5 V to +20.0 V Input voltage range, all inputs -05 V to VCC+ 0.5 V Maximum DC input current, any one input

8、. 10 mA Maximum power dissipation per package, (PD): TA= -55C to +100C. 500 mW TA= +100C to +125C 1/ Maximum device dissipation per output transistor, for TA= full package temperature range (all package types) 100 mW Operating temperature range, (TA) . -55C to +125C Maximum package thermal impedance

9、 (JA) 91.1C/W 2/ Storage temperature range, (TSTG) -85C to +150C Maximum lead temperature (during soldering) , at distance 1/16 1/32 inch (1.59 0.79 mm) from case for 10 s max . +265C 1/ Derate linearly at 12 mW/C to 200 nW. 2/ The package thermal impedance is calculated in accordance with JESD 51-7

10、. Provided by IHSNot for Resale-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09606 REV PAGE 3 1.4. Recommended operating conditions. 3/ 4/ Supply voltage range, (for TA= full package temperature range) (VDD) . +5.0 V to +18.0 V 2. APPLICABLE DOCUMENTS JE

11、DEC PUB 95 Registered and Standard Outlines for Semiconductor Devices JESD 51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or at h

12、ttp:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit contai

13、ner shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction,

14、 and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Block diagra

15、m. The block diagram shall be as shown in figure 3. _ 3/ For maximum reliability, nominal operating conditions should be selected so that operation is always within the recommended range. 4/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The

16、 manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. Provided by IHSNot for Resale-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09606 REV PAGE 4 TABLE I. Electrical performance characteristic

17、s. 1/ Conditions 2/ Limits at indicated temperatures (C) +25 Test Symbol VO(V) VIN(V) VCC(V) VCC(V) -55 -40 +85 +125 Min Max Unit 0, 5 5 5 1.5 1.5 1.5 1.5 1.5 0, 10 5 10 2 2 2 2 2 mA 0, 15 5 15 4 4 120 120 4 Quiescent device current, IDDmax and ICCin CMOS-CMOS mode 0, 20 5 20 20 20 600 600 20 A 0, 5

18、 5 5 5 5 6 6 5 0, 10 5 10 5 5 6 6 5 Quiescent device current, ICCmax TTL-CMOS mode 0, 15 5 15 5 5 6 6 5 mA 0.4 0, 5 5 0.64 0.61 0.42 0.36 0.51 0.5 0, 10 10 1.6 1.5 1.1 0.9 1.3 Output low (sink) current, IOLmin 1.5 0, 15 15 4.2 4 2.8 2.4 3.4 4.6 0, 5 5 -0.64 -0.61 -0.42 -0.36 -0.51 2.5 0, 5 5 -2 -1.8

19、 -1.3 -1.15 -1.6 9.5 0, 10 10 -1.6 -1.5 -1.1 -0.9 -1.3 Output low (source) current, IOHmin 13.5 0, 15 15 -4.2 -4 -2.8 -2.4 -3.4 mA 0, 5 5 0.05 0.05 0, 10 10 0.05 0.05 Output voltage: low level, VOLmax 0, 15 15 0.05 0.05 0, 5 5 4.95 4.95 0, 10 10 9.95 9.95 Output voltage: high level, VOHmin 0, 15 15

20、14.95 14.95 TTL-CMOS 1 5 10 0.8 0.8 TTL-CMOS 1 5 15 0.8 0.8 CMOS-CMOS 1 5 10 1.5 1.5 CMOS-CMOS 1.5 5 15 1.5 1.5 Input low voltage, VILmax 3/ CMOS-CMOS 1.5 10 15 3 3 TTL-CMOS 9 5 10 2 2 TTL-CMOS 13.5 5 15 2 2 CMOS-CMOS 9 5 10 3.5 3.5 CMOS-CMOS 13.5 5 15 3.5 3.5 Input high voltage, VIHmin 3/ CMOS-CMOS

21、 13.5 10 15 7 7 V Input current, IINmax 0, 18 18 0.1 0.1 1 1 0.1 A See footnote at end of the table. Provided by IHSNot for Resale-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09606 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Limits Te

22、st Symbol Conditions 4/ VCC(V) VDD (V) Min Max Unit 5 10 280 From TTL to CMOS VDD VCC5 15 280 5 10 240 5 15 240 From CMOS to CMOS VDD VCC10 15 140 10 5 550 15 5 550 Propagation delay: high to low From CMOS to CMOS tPHLVCC VDD15 10 140 ns 5 10 280 From TTL to CMOS VDD VCC5 15 280 5 10 240 5 15 240 Fr

23、om CMOS to CMOS VDD VCC10 15 140 10 5 400 15 5 400 Propagation delay: high to low From CMOS to CMOS tPLHVCC VDD15 10 120 ns 5 200 10 100 Transition time tTHL, tTLHAll modes 15 80 ns Input capacitance CINAny input 7.5 pF 1. Testing and other quality control techniques are used to the extent deemed ne

24、cessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/

25、or design. 2. Over recommended operating free air temperature range (unless otherwise noted). 3. Applies to the six input signals. For mode control (P13), only the CMOS-CMOS ratings apply 4. TA= 25C, Input tr, tf= 20 ns, CL= 50 pF, RL= 200 . Provided by IHSNot for Resale-,-,-DEFENSE SUPPLY CENTER, C

26、OLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09606 REV PAGE 6 Case X Dimensions Symbol Min Max Symbol Min Max A 1.20 e 0.65 BSC A1 0.05 0.15 E 4.30 4.50 b 0.19 0.30 E1 6.20 6.60 c 0.15 NOM L 0.50 0.75 D 4.90 5.10 Notes: 1. All linear dimensions are in millimeters. 2. This drawing i

27、s subject to change without notice. 3. Body dimensions do not include mold flash or protrusion not to exceed 0.15. 4. Fall within JEDEC MO-153. FIGURE 1. Case outlines. Provided by IHSNot for Resale-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09606 REV

28、PAGE 7 Pin No. Signal name Pin No. Signal name 1 1DIR 9 2 OE 2 1B1 10 2A8 3 1B2 11 2A7 4 GND 12 GND 5 1B3 13 2A6 6 1B4 14 2A5 7 VCCB 15 VCCA8 1B5 16 2A4 FIGURE 2. Terminal connections. FIGURE 3. Block diagram. Provided by IHSNot for Resale-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CO

29、DE IDENT NO. 16236 DWG NO. V62/09606 REV PAGE 8 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensit

30、ive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensiti

31、ve devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to m

32、ake changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item

33、drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number Top side marking V62/09606-01XE 01295 CD4504BMPWREP 4504BEP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS