DLA DSCC-DWG-V62 12663-2013 MICROCIRCUIT DIGITAL-LINEAR QUAD CURRENT OUTPUT SERIAL INPUT 16 BIT DIGITAL TO ANALOG CONVERTER MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY RICK OFFICER DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ Origi

2、nal date of drawing YY-MM-DD CHECKED BY RAJESH PITHADIA TITLE MICROCIRCUIT, DIGITAL-LINEAR, QUAD, CURRENT OUTPUT, SERIAL INPUT 16 BIT DIGITAL TO ANALOG CONVERTER, MONOLITHIC SILICON 13-03-28 APPROVED BY CHARLES F. SAFFLE SIZE A CODE IDENT. NO. 16236 DWG NO. V62/12663 REV PAGE 1 OF 13 AMSC N/A 5962-V

3、004-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12663 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance quad, curre

4、nt output, serial input 16 bit digital to analog converter microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control num

5、ber for identifying the item on the engineering documentation: V62/12663 - 01 X B Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 AD5544 Quad, current output, serial input 16 bit digital to analog c

6、onverter 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 28 MO-150-AH Small outline package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Fini

7、sh designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12663 REV PA

8、GE 3 1.3 Absolute maximum ratings. 1/ Positive power supply (VDD) to ground (GND) . -0.3 V, +8 V Negative power supply (VSS) to GND +0.3 V, -7 V Reference voltage input (VREFx) to GND -18 V, +18 V Logic input and output to GND . -0.3 V, +8 V Voltage at current output (V(IOUTx) to GND . -0.3 V, VDD+

9、0.3 V Analog ground (AGNDx) to digital ground (DGND) . -0.3 V, +0.3 V Input current to any pin except supplies . 50 mA Power dissipation (PD) . See table I. Maximum junction temperature range (TJ) . 150C Storage temperature range (TSTG) -65C to +150C Lead temperature: Vapor phase, 60 seconds 215C In

10、frared, 15 seconds 220C 1.4 Recommended operating conditions. 2/ Positive power supply (VDD) 2.7 V to 5.5 V Operating free-air temperature range (TA) . -55C to +125C 1.5 Thermal characteristics. Thermal resistance, junction to ambient (JA) 100C/W 1/ Stresses beyond those listed under “absolute maxim

11、um rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended perio

12、ds may affect device reliability. 2/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. Provided by IHSNot for ResaleNo reprod

13、uction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12663 REV PAGE 4 2. APPLICABLE DOCUMENTS JEDEC Solid State Technology Association JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Applicat

14、ions for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as fol

15、lows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended op

16、erating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as

17、shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Timing waveforms. The timing waveforms shall be as shown in figure 3. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND

18、MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12663 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/Temperature, TADevice type Limits Unit Min Max Static performance. 3/ Resolution N 1 LSB = VREF/ 216= 153 V when VREF= 10 V -55C to +125C 01 1

19、6 Bits Relative accuracy INL -55C to +125C 01 1.5 LSB Differential nonlinearity DNL -55C to +125C 01 1.5 LSB Output leakage current IOUTData = 0x0000 +25C 01 10 nA +85C 20 Full scale gain error GFSEData = 0xFFFF -55C to +125C 01 4 mV Full scale 4/ temperature coefficient TCVFS-55C to +125C 01 1 typi

20、cal ppm/ C Feedback resistor RFBx VDD= 5 V -55C to +125C 01 4 8 k Reference input. VREFx range VREFx -55C to +125C 01 -15 +15 V Input resistance RREFx -55C to +125C 01 4 8 k Input resistance match RREFx Channel to channel -55C to +125C 01 0.35 typical % Input capacitance 4/ CREFx -55C to +125C 01 5

21、typical pF Analog output. Output current IOUTx Data = 0xFFFF -55C to +125C 01 1.25 2.5 mA Output capacitance 4/ COUTx Code dependent -55C to +125C 01 35 typical pF Logic inputs and output. Logic input low voltage VIL-55C to +125C 01 0.8 V Logic input high voltage VIH-55C to +125C 01 2.4 V Input leak

22、age current IIL-55C to +125C 01 1 A Input capacitance 4/ CIL-55C to +125C 01 10 pF See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12663 REV P

23、AGE 6 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/Temperature, TADevice type Limits Unit Min Max Logic inputs and output continued. Logic output low voltage VOLIOL= 1.6 mA -55C to +125C 01 0.4 V Logic output high voltage VOHIOH= 100 A -55C to +125C 01 4 V I

24、nterface timing. 4/ 5/ Clock width high tCH-55C to +125C 01 25 ns Clock width low tCL-55C to +125C 01 25 ns CS to clock setup tCSS-55C to +125C 01 0 ns Clock to CS hold tCSH-55C to +125C 01 25 ns Clock to SDO propagation delay tPD-55C to +125C 01 2 20 ns Load DAC pulse width tLDAC-55C to +125C 01 25

25、 ns Data setup tDS-55C to +125C 01 20 ns Data hold tDH-55C to +125C 01 20 ns Load setup tLDS-55C to +125C 01 5 ns Load hold tLDH-55C to +125C 01 25 ns Supply characteristics. Power supply range VDD RANGE-55C to +125C 01 2.7 5.5 V Positive supply current IDDLogic inputs = 0 V -55C to +125C 01 5 A Neg

26、ative supply current ISSLogic inputs = 0 V, VSS= -5 V -55C to +125C 01 9 A Power dissipation PDLogic inputs = 0 V -55C to +125C 01 1.25 mW Power supply sensitivity PSS VDD= 5% -55C to +125C 01 0.006 %/% See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitt

27、ed without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12663 REV PAGE 7 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/Temperature, TADevice type Limits Unit Min Max AC characteristics. 6/ Output voltage se

28、ttling time tSTo 0.1% of full scale, data = 0x0000 to 0xFFFF to 0x0000 -55C to +125C 01 0.9 typical s Reference multiplying bandwidth BW 3 dB VREFx = 5 Vp-p, data = 0xFFFF, CFB= 2.0 pF -55C to +125C 01 12 typical MHz DAC glitch impulse Q VREFx = 8 V rms, data = 0x0000 to 0x8000 to 0x0000 -55C to +12

29、5C 01 -1 typical nV-sec Feedthrough error VOUTx/ VREFx Data = 0x0000, VREFx = 100 mV rms, f = 100 kHz -55C to +125C 01 -65 typical dB Crosstalk error VOUTA/ VREFB Data = 0x0000, VREFB = 100 mV rms, adjacent channel, f = 100 kHz -55C to +125C 01 -90 typical dB Digital feedthrough Q CS = 1, fCLK= 1 MH

30、z -55C to +125C 01 0.6 typical nV-sec Total harmonic distortion THD VREFx = 5 Vpp, data = 0xFFFF, f = 1 kHz -55C to +125C 01 -98 typical dB Output spot noise voltage eNf = 1 kHz, BW = 1 Hz -55C to +125C 01 7 typical nV / Hz1/ Testing and other quality control techniques are used to the extent deemed

31、 necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization a

32、nd/or design. 2/ Unless otherwise specified, VDD= 2.7 V to 5.5 V, VSS= 0 V, IOUTx = virtual GND, AGNDx = 0 V, VREFA = VREFB = VREFC = VREFD =10 V, and TA= full temperature range. 3/ All static performance tests (except IOUTx) are performed in a closed loop system using an external precision OP177 cu

33、rrent to voltage amplifier. The device RFBterminal is tied to the amplifier output. Typical values represent average readings measured at 25C. 4/ These parameters are guaranteed by design and are not subject to production testing. 5/ All input control signals are specified with tR= tF= 2.5 ns (10% t

34、o 90% of 3 V) and timed from a voltage level of 1.5 V. 6/ All ac characteristic tests are performed in a closed loop system using an AD8038 current to voltage converter amplifier. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME

35、COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12663 REV PAGE 8 Case X FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12663 REV PAGE 9 Case

36、X Symbol Dimensions Inches Millimeters Min Med Max Min Med Max A - - .078 - - 2.00 A1 .064 .068 .072 1.65 1.75 1.85 A2 .001 - .003 0.05 - 0.10 b .008 - .014 0.22 - 0.38 c .003 - .009 0.09 - 0.25 D .389 .401 .413 9.90 10.20 10.50 E .196 .208 .220 5.00 5.30 5.60 E1 .291 .307 .322 7.40 7.80 8.20 e .025

37、 BSC 0.65 BSC L .021 .029 .037 0.55 0.75 0.95 NOTES: 1. Controlling dimensions are inch, millimeter dimensions are given for reference only. 2. Falls within reference to JEDEC MO-150-AH. FIGURE 1. Case outline - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without

38、license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12663 REV PAGE 10 Device type 01 Case outline X Terminal number Terminal symbol Description 1 AGNDA DAC A analog ground. 2 IOUTA DAC A current output. 3 VREFA DAC A reference voltage input terminal. Est

39、ablishes DAC A full scale output voltage. This pin can be tied to the VDDpin. 4 RFBA Establish the voltage output for DAC A by connecting to an external amplifier output. 5 MSB MSB pin. Set pin during a reset pulse (RS ) or at system power on if tied to ground or VDD. 6 RS Reset pin, active low inpu

40、t. Input register and DAC registers are set to all 0s or half scale code, determined by the voltage on the MSB pin. Register data = 0x0000 when MSB = 0. 7 VDDPositive power supply input. Specified range of operation: 5 V 10 %. 8 CS Chip select, active low input. Disable shift register loading when h

41、igh. Transfers serial register data to the input register when CS / LDAC returns high. Does not affect LDAC operation. 9 CLK Clock input. Positive edge clocks data into the shift register. 10 SDI Serial data input. Input data loads directly into the shift register. 11 RFBB Establish the voltage outp

42、ut for DAC B by connecting to an external amplifier output. 12 VREFB DAC B reference voltage input terminal. Establishes DAC B full scale output voltage. This pin can be tied to the VDDpin. 13 IOUTB DAC B current output. 14 AGNDB DAC B analog ground. FIGURE 2. Terminal connections. Provided by IHSNo

43、t for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12663 REV PAGE 11 Device type 01 Case outline X Terminal number Terminal symbol Description 15 AGNDC DAC C analog ground. 16 IOUTC DAC C curre

44、nt output. 17 VREFC DAC C reference voltage input terminal. Establishes DAC C full scale output voltage. This pin can be tied to the VDDpin. 18 RFBC Establish the voltage output for the DAC C by connecting to an external amplifier output. 19 NC No connect. Do not connect to this pin. 20 SDO Serial d

45、ata output. Input data loads directly into the shift register. Data appears at SDO at 19 clock pulses for the device after input at the SDI pin. 21 LDAC Load DAC register strobe, level sensitive active low. Transfer all input register data to DAC registers. Asynchronous active low input. 22 AGNDF Hi

46、gh current analog force ground. 23 VSSNegative bias power supply input. Specified range of operation: -5.5 V to +0.3 V. 24 DGND Digital ground pin. 25 RFBD Establish the voltage output for DAC D by connecting to an external amplifier output. 26 VREFD DAC D reference voltage input terminal. Establish

47、es DAC D full scale output voltage. This pin can be tied to the VDDpin. 27 IOUTD DAC D current output. 28 AGNDD DACD analog ground. FIGURE 2. Terminal connections - continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12663 REV PAGE 12 FIGURE 3. Timing waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without lice