DLA DSCC-DWG-V62 13622-2013 MICROCIRCUIT DIGITAL-LINEAR PWM SYSTEM CONTROLLER WITH 4-BIT 6-BIT OR 8- BIT VID SUPPORT MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ Orig

2、inal date of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL-LINEAR, PWM SYSTEM CONTROLLER WITH 4-BIT, 6-BIT, OR 8-BIT VID SUPPORT, MONOLITHIC SILICON 13-12-11 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/13622 REV PAGE 1 OF 13 AMSC N/A 5962-V024-14 Provi

3、ded by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13622 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance digital PWM system cont

4、roller with 4-bit, 6-bit, or 8-bit VID support microcircuit, with an operating temperature range of -55C to +115C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for iden

5、tifying the item on the engineering documentation: V62/13622 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 UCD9222 -EP Digital PWM system controller with 4-bit, 6-bit, or 8-bit VID suppor

6、t 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 48 JEDEC MO-220 Plastic quad flatpack no-lead 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Fi

7、nish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13622 REV

8、PAGE 3 1.3 Absolute maximum ratings. 1/ Voltage applied at V33Dto DGND -0.3 V to 3.8 V Voltage applied at V33Dto AGND -0.3 V to 3.8 V Voltage applied at to any pin . -0.3 V to 3.8 V 2/ Storage temperature range . -55C to 150C 1.4 Recommended operating conditions. Supply voltage during operation, V33

9、D, V33DIO, V33A(V) 3.0 V to 3.6 V Operating junction temperature range . -55C to 115C Maximum junction temperature . 125C 1.5 Thermal characteristics. Thermal metric 3/ Case outline X Units Junction to ambient thermal resistance, JA4/ 27.1 C/W Junction to case (top) thermal resistance, JCtop5/ 12.9

10、Junction to board thermal resistance, JB6/ 4.3 Junction to top characterization parameter, JT7/ 0.2 Junction to board characterization parameter, JB8/ 4.3 Junction to case (bottom) thermal resistance, JCbot9/ 0.6 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent da

11、mage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

12、 2/ All voltage referenced to GND. 3/ For more information about traditional and new thermal metrics, see manufacturer data. 4/ The junction to ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K-board, as specified in JESD51-7, in an environme

13、nt described in JESD51-2a. 5/ The junction to case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specified JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. 6/ The junction to board thermal resistance is

14、obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. 7/ The junction to top characterization parameter, JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtai

15、ning JA, using a procedure described in JESD51-2a (sections 6 and 7). 8/ The junction to board characterization parameter, JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (section

16、s 6 and 7). 9/ The junction to case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specified JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88 Provided by IHSNot for ResaleNo reproduction or netw

17、orking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13622 REV PAGE 4 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices JESD51 Methodology for

18、 the Thermal Measurement of Component Packages (Single Semiconductor Device). JESD51-2a Integrated Circuits Thermal Test Method Environment Conditions Natural Convection (Still Air) JESD51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages JESD51-8 Integrated Circuits

19、 Thermal Test Method Environment Conditions Junction-to-board (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201-2107). AMERICAN NATIONAL STANDARDS INSTITUTE (ANSI) STANDARD

20、ANSI SEMI STANDARD G30-88 null Test Method for Junction-to-Case Thermal Resistance Measurements for Ceramic Packages (Applications for copies should be addressed to the American National Standards Institute, Semiconductor Equipment and Materials International, 1819 L Street, NW, 6 th floor, Washingt

21、on, DC 20036 or online at http:/www.ansi.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit

22、container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein.

23、 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal function. The terminal function shall be as shown in figure 2. Prov

24、ided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13622 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Test conditions 2/ Limits Unit Min Typ Max Suppl

25、y current Supply current IV33Total V33 supply current, V33A= V33DIO= 3.3 V 54 80 mA IV33DIOV33DIO= 3.3 V 42 55 IV33A V33A= 3.3 V 8 15 IV33DV33D= 3.3 V storing configuration parameters in flash memory 52 65 Internal regulator controller Inputs/Outputs 3.3 V linear regulator V33Emitter of NPN transist

26、or 3.25 3.3 3.6 V 3.3 V linear regulator feedback V33FB4 4.6 Series pass base driver IV33FBVIN = 12 V 0.2 0.4 8 mA Series NPN pass device Beta 40 100 External supplied 3.3 V power Digital 3.3 V power V33D, V33DIO1, V33DIO2TJ= 25C 3.0 3.6 V Analog 3.3 V power V33ATJ= 25C 3.0 3.6 Error amplifier input

27、s EAPn, EANn Common mode voltage each pin VCM0 1.8 V Internal error voltage range VERRORAFE_GAIN field of CLA_GAINS = 1X 3/ -256 248 mV Error voltage digital resolution EAP-EAN AFE_GAIN field of CLA_GAINS = 8X 1 mV Input impedance REAGround reference, TJ= 25C 1.5 M Input offset current IOFFSET1 k so

28、urce impedance -5 5 A Vref 10 bit DAC Reference voltage setpoint Vref0 1.7 V Reference voltage resolution Vrefres1.56 mV Analog input CS1A, CS2A, VinMon, IinMon, Vtrack, Temp1, Temp2, Addr0, Adrr1 Measurement range for voltage monitoring VADC_RANGEInputs: VinMon, IinMon, Vtrack, Temp1, Temp2, CS1A,

29、CS2A 0 2.6 V Input offset voltage Voffset -27 27 mV Over current comparator threshold voltage range 4/ VOC_THRSInputs: CS1A, CS2A 0.032 2 V Over current comparator threshold voltage range VOC_RESInputs: CS1A, CS2A 31.25 mV Int. temperature sense accuracy TempinternalOver range from 0C to 100C -15 15

30、 C ADC integral nonlinearity INL TJ= -40C to 115C -2.5 2.5 mV Input leakage current IIkg3V applied to pin 100 nA Input impedance RINGround reference 8 M Current sense input capacitance CIN10 pF See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without

31、 license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13622 REV PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions Limits Unit Min Max Digital Inputs/Outputs Low level output voltage VOLIOL= 6 mA 5/, V33DIO=

32、 3 V Dgnd + 0.3 V High level output voltage VOHIOH= -6 mA 6/, V33DIO= 3 V V33DIO0.6V High level input voltage VIHV33DIO= 3V 2.1 3.6 Low level input voltage VILV33DIO= 3.5 V 1.4 System performance Voltage where device comes out of reset VRESETV33DPin 2.3 2.4 V Pulse width need for reset tRESETnRESET

33、pin 2 s Setpoint reference accuracy VRefAccVref commanded to be 1V, at 25C AFEgain = 4, 1V input to EAP/N measured at output of the EADC 7/ -10 10 mV Setpoint reference accuracy over temperature -55C to 115C -40 40 mV Differential offset between gain settings VDiffOffsetAFEgain = 4 compared to AFEga

34、in = 1, 2, or 8 -4 4 mV Digital compensator delay tDelay240 240 + 1 switching cycle ns Switching frequency FSW15.260 2000 kHz Accuracy -5% 5% Max and Min duty cycle Duty 0% 100% Minimum V33 slew rate V33SlewV33 slew rate between 2.3 V and 2.9 V, TJ= -40C to 115C 0.25 V/ms Retention of configuration

35、parameters 8/ tretentionTJ= 25C 100 Years Number of nonvolatile erase/write cycles Write_ Cycles TJ= 25C 20 K cycles Max VID message rate RateVIDAll rails configured to accept 4-bit VID messages 9/ 1 msg/ msec All rails configured to accept 6-bit VID messages 9/ 4 All rails configured to accept 8-bi

36、t VID messages 10/ 4 See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13622 REV PAGE 7 TABLE I. Electrical performance characteristics - Continu

37、ed. 1/ Test Symbol Test conditions Limits Unit Min Typ Max ADC monitoring intervals and response times ADC single sample time tADC3.84 s ADC sequencer interval tADC_SEQMin = 2 x 1 Rail + 6 = 8 samples Max = 2 x 2 Rail + 6 = 10 samples 30.72 38.40 Output voltage monitoring interval tVOUT200 Output cu

38、rrent monitoring interval tIOUT200 x NRailsInput voltage monitoring interval tVIN1 ms Input current monitoring interval tIIN1 Temperature monitoring interval tTEMP100 Auxiliary ADC monitoring interval tAUXADC100 Test Symbol Test conditions Limits Unit Typ MAX no VID Max /w VID 11/ ADC monitoring int

39、ervals and response times - Continued Over/under voltage fault response time during normal operation tOVF, tUVFNormal regulation, no PMBus activity 4 stages enabled 250 800 s Over/under voltage fault response time during data logging tOVF, tUVFDuring data logging to nonvolatile memory 12/ 800 1000 O

40、ver/under voltage fault response time, when tracking or sequencing enable tOVF, tUVFDuring tracking and soft start ramp 400 Over/under current fault response time during normal operation tOCF, tUCFNormal regulation, no PMBus activity, 4 stages enabled 75% to 125% current step 13/ 100 + (600 x NRails

41、) 5000 Over/under current fault response time during data logging tOCF, tUCFDuring data logging to nonvolatile memory 75% to 125% current step 600 + (600 x NRails) 5000 Over temperature fault response time tOTFTemperature rise of 10C, at OT threshold 1.60 sec Time to tristate the PWM output after a

42、shutdown is initiated t3-StateDRIVER_CONFIG = 0x01 5.5 s See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13622 REV PAGE 8 TABLE I. Electrical p

43、erformance characteristics - Continued. 1/ Test Symbol Test conditions Limits Unit Min Typ Max Hardware fault detection latency Time to disable DPWM output base on active FAULT pin signal tFAULTHigh level on FAULT pin 18 s Time to disable DPWM A output base on internal analog comparator tCLFStep cha

44、nge in CS voltage from 0 V to 2.5 V 4 Switch Cycles I2C/SMBus/PMBus timing requirements 14/ SMBus/PMBus operating frequency fSMBSlave mode; SMBC 50% duty cycle 10 1000 kHz I2C operating frequency fI2CSlave mode; SCL 50% duty cycle 10 1000 Bus free time between start and stop t(BUF)5 s Hold time afte

45、r (repeated) start t(HD:STA)0.3 Repeated start setup time t(SU:STA)0.3 Stop setup time t(SU:STO)0.3 Data hold time t(HD:DAT)Receive mode 0 ns Data setup time t(SU:DAT)55 Error signal/detect t(TIMEOUT)See 15/ 35 ms Clock low period t(LOW)0.55 s Clock high period t(HIGH)See 16/ 0.3 50 Cumulative clock

46、 low slave extend time t(LOW:SEXT)See 17/ 25 ms Clock/data fall time tFALLRise time tRISE= (VILMAX 0.15) to (VIHMIN+ 0.15), TJ= -40C to 115C 1000 ns Clock/data rise time tRISEFall time tFALL= 0.9 V33to (VILMAX 0.15) TJ= -40C to 115C 1000 CINSee footnote at end of table. Provided by IHSNot for Resale

47、No reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13622 REV PAGE 9 TABLE I. Electrical performance characteristics - Continued. 1/ 1/ Testing and other quality control techniques are used to the extent de

48、emed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Over operating junction temperature ra