DLA DSCC-VID-V62 03611 REV B-2012 MICROCIRCUIT DIGITAL CMOS HIGH-SPEED SERIAL-BUS LINK-LAYER CONTROLLER MONOLITHIC SILICON.pdf

1、 REVISIONSLTR DESCRIPTION DATE APPROVEDA Update boilerplate to current revision. - CFS 07-09-12 Thomas M. Hess B Update boilerplate paragraphs to current requirements. - PHN 12-04-10 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 432

2、18-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV B B B B B B B B B B B B B B B B B PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY Charles F. Saffle DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original dat

3、e of drawing CHECKED BY Thomas M. Hess TITLE MICROCIRCUIT, DIGITAL, CMOS, HIGH-SPEED SERIAL-BUS LINK-LAYER CONTROLLER, MONOLITHIC SILICON YY-MM-DD 02-12-12 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/03611 REV B PAGE 1 OF 17 AMSC N/A 5962-V052-12 Provided by IHSNot for Resale

4、No reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03611 REV B PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance high-speed serial-bus link-layer co

5、ntroller microcircuit, with an operating temperature range of -40C to +85C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering doc

6、umentation: V62/03611 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 TSB12LV01B-EP High-Speed Serial-Bus Link-Layer Controller 1.2.2 Case outline(s). The case outlines are as specified her

7、ein. Outline letter Number of pins JEDEC PUB 95 Package style X 100 JEDEC MS-026 Plastic Quad Flatpack 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plate

8、D PalladiumE Gold flash palladium Z Other 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to +3.6 V Supply voltage range (VCC5V) . -0.5 V to +5.5 V Input voltage range (VI) . -0.5 V to VCC+ 0.5 V Output voltage range (VO) . -0.5 V to VCC+ 0.5 V Input clamp current (IIK) (VIVCC)

9、20 mA 2/ Output clamp current (IOK) (VOVCC) 20 mA 3/ Maximum power dissipation: TA +25C . 1500 mW TA +70C . 739.5 mW TA +85C . 486 mW Operating free-air temperature range (TA) -40C to +85C Storage temperature range (TSTG) . -65C to +150C 1/ Stresses beyond those listed under “absolute maximum rating

10、” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may af

11、fect device reliability. 2/ This applies to external input and bidirectional buffers. For 5 V tolerant terminals, use VI VCC5V. 3/ This applies to external output and bidirectional buffers. For 5 V tolerant terminals, use VO VCC5V. Provided by IHSNot for ResaleNo reproduction or networking permitted

12、 without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03611 REV B PAGE 3 1.4 Recommended operating conditions. 4/ Supply voltage range (VCC) . +3.0 V to +3.6 V Supply voltage range (VCC5V): (5 V tolerant) +3.0 V to +5.5 V (Non 5 V tolera

13、nt) +3.0 V to +3.6 V Minimum high level input voltage (VIH) +2.0 V Maximum low level input voltage (VIL) . +0.8 V Transition time (tt) (10% to 90%) . 0 to 6 ns Operating free-air temperature range (TA) -40C to +85C Junction temperature range (TJ) 0C to +115C 5/ 2. APPLICABLE DOCUMENTS JEDEC SOLID ST

14、ATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) THE INSTITUTE OF ELEC

15、TRICAL AND ELECTRONICS ENGINEERS (IEEE) IEEE 1394-1995 - (1394) Standard for High-Performance Serial Bus (Copies of these documents are available online at http:/www.ieee.org or from the IEEE Service Center, 445 Hoes Lane, P.O. Box 1331, Piscataway, NJ 088551331. 4/ Use of this product beyond the ma

16、nufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 5/ The junction temperatures listed reflect simulation conditions. The absolute maximum junction temperature

17、 is 150C. The customer is responsible for verifying the junction temperature. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03611 REV B PAGE 4 3. REQUIREMENTS 3.

18、1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufactu

19、rers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, c

20、onstruction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Block diagram. The block diagram shall be as shown in figure 2. 3.5.3 Terminal connections. The terminal connections shall be as shown in fi

21、gure 3. 3.5.4 Timing waveforms. The timing waveforms shall be as shown in figure 4. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03611 REV B PAGE 5 TABLE I. Ele

22、ctrical performance characteristics. 1/ Test Symbol Test conditions unless otherwise specified VCCTemperature, TALimits Unit Min Max High level output voltage VOHIOH= -8 mA 2/ 3.0 V and 3.6 V -40C to +85C VCC 0.6 V IOH= -4 mA 3/ VCC 0.6 Low level output voltage VOLIOL= 8 mA 2/ 3.0 V and 3.6 V 0.5 V

23、IOL= 4 mA 3/ 0.5 Low level input current IIL4/ VI= GND TTL/LVCMOS 3.0 V and 3.6 V -1 A 5-V tolerant 3.0 V and 3.6 V -20 D0-D7, CTL0, CTL1 3.0 V and 3.6 V -20 High level input current IIHVI= VCCTTL/LVCMOS 3.0 V and 3.6 V 1 A VI= VCC, 5V 5-V tolerant 3.0 V and 3.6 V 20 D0-D7, CTL0, CTL1 3.0 V and 3.6

24、V 20 High-impedance state output current IOZ5/ VO= VCCor GND 3.0 V and 3.6 V 20 A Static supply current ICC(Q)IO= 0 3.0 V and 3.6 V 88 TYP A Dynamic supply current ICC(Dynamic)3.0 V and 3.6 V 120 TYP mA See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitt

25、ed without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03611 REV B PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions unless otherwise specified VCCTemperature, TA Limits Unit Min Max Host

26、-Interface Timing Requirements 6/ Cycle time, BCLK tc1See figure 4. 3.0 V and 3.6 V +25C 20 111 ns Pulse duration, BCLK high tw1(H)8.6Pulse duration, BCLK low tw1(L)ns Setup time, DATA0-DATA31 valid before BCLK tsu14 Hold time, DATA0-DATA31 valid after BCLK th12 ns Setup time, ADDR0-ADDR7 valid befo

27、re BCLK tsu28 Hold time, ADDR0-ADDR7 valid after BCLK th2ns Setup time, CS low before BCLK tsu3Hold time, CS low after BCLK th3 2 ns Setup time, WR valid before BCLK tsu4 8 Hold time, WR valid after BCLK th4 ns Host-Interface Switching Characteristics Delay time, BCLK to CA td1 See figure 4 CL= 45 p

28、F 3.0 V and 3.6 V -40C to +85C 2.5 8 ns Delay time, BCLK to CA td2 2.5 8 Delay time, BCLK to DATA0-DATA31 valid td36/ 2.5 10 ns Delay time, BCLK to DATA0-DATA31 invalid td4 6/ 2.5 10 ns Cable PHY-Layer-Interface Timing Requirements 6/ Cycle time, SCLK tc2See figure 4. 3.0 V and 3.6 V -40C to +85C 20

29、.347 20.343 ns Pulse duration, SCLK high tw2(H)9 Pulse duration, SCLK low tw2(L)ns Setup time, D0-D7 valid before SCLK tsu5 4 Hold time, D0-D7 valid after SCLK th5 0 ns Setup time, CTL0-CTL1 valid before SCLK tsu6Hold time, CTL0-CTL1 valid after SCLK th6 ns See footnotes at end of table Provided by

30、IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03611 REV B PAGE 7 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions unless otherwise

31、 specified VCC Temperature, TALimits Min Max Cable PHY-Layer-Interface Switching Characteristics 6/ Delay time, SCLK to D0-D7 valid td5 See figure 4 CL= 45 pF 3.0 V and 3.6 V -40C to +85C 1 11 ns Delay time, SCLK to D0-D7 invalid td6 1 11Delay time, SCLK to D0-D7 invalid td7 11 ns Delay time, SCLK t

32、o CTL0-CTL1 valid td8 11Delay time, SCLK to CTL0-CTL1 invalid td9 11 ns Delay time, SCLK to CTL0-CTL1 invalid td10 1 11Delay time, SCLK to LREQ td11 11 ns Miscellaneous Timing Requirements 6/ Cycle time, CYCLEIN tc3See figure 4. 3.0 V and 3.6 V -40C to +85C 124.99 125.01 s Pulse duration, CYCLEIN hi

33、gh tw3(H)0.08 120 s Pulse duration, CYCLEIN low tw3(L)4 s Miscellaneous Signal Switching Characteristics 6/ Delay time, SCLK to INT td12 See figure 4. 3.0 V and 3.6 V -40C to +85C 4 18 ns Delay time, SCLK to INT td13 4 18 ns Delay time, SCLK to CYCLEOUT td14 4 16 ns Delay time, SCLK to CYCLEOUT td15

34、 4 16 ns 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absenc

35、e of specific parametric testing, product performance is assured by characterization and/or design. 2/ This test condition is for terminals D0-D7, CTL0, CTL1, and POWERON. 3/ This test condition is for terminals DATA0-DATA31, CA, INT, CYCLEOUT, GRFEMP, CYDNE, and CYST. 4/ This specification only app

36、lies when pull-up and pull-down terminator is turned off. 5/ Three-state output must be in high-impedance mode. 6/ These parameters are not production tested. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, O

37、HIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03611 REV B PAGE 8 Case X Dimensions Symbol Inches Millimeters Symbol Inches Millimeters Min Max Min Max Min Max Min Max A 0.047 1.20 D1 0.543 0.559 13.80 14.20 A1 0.053 0.057 1.35 1.45 D2 0.472 TYP 12.00 TYP A2 0.010 TYP 0.25 TYP E 0.622 0.638 15.80 16.20

38、 A3 0.002 0.05 E1 0.543 0.559 13.80 14.20 b 0.007 0.011 0.17 0.27 e 0.020 TYP 0.50 TYP C 0.005 NOM 0.13 NOM K 0.018 0.030 0.45 0.75 D 0.622 0.638 15.80 16.20 NOTES: 1. This drawing is subject to change without notice. 2. Falls within JEDEC MS-026. 3. All linear dimensions are shown in millimeters. F

39、IGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03611 REV B PAGE 9 FIGURE 2. Block diagram. Provided by IHSNot for ResaleNo reproduction or

40、networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03611 REV B PAGE 10 Device type 01 Case outline X Terminal number Terminal symbol Terminal number Terminal symbol Terminal number Terminal symbol Terminal number T

41、erminal symbol 1 GND 26 VCC51 GND 76 POWERON 2 DATA16 27 ADDR4 52 D7 77 MTEST3 3 DATA17 28 ADDR5 53 D6 78 GND 4 DATA18 29 ADDR6 54 D5 79 GND 5 DATA19 30 ADDR7 55 D4 80 GND 6 VCC31 GND 56 VCC81 GND 7 DATA20 32 BCLK 57 D3 82 DATA0 8 DATA21 33 VCC+5 58 D2 83 DATA1 9 DATA22 34 CS 59 D1 84 DATA210 DATA23

42、 35 CA 60 D0 85 DATA3 11 GND 36 WR 61 GND 86 VCC+5 12 DATA24 37 INT 62 CTL1 87 DATA4 13 DATA25 38 GND 63 CTL0 88 DATA5 14 DATA26 39 RESET 64 VCC+5 89 DATA6 15 DATA27 40 GND 65 SCLK 90 DATA7 16 VCC+5V 41 GND 66 GND 91 GND 17 DATA28 42 CYCLEIN 67 LREQ 92 DATA8 18 DATA29 43 VCC68 GND 93 DATA9 19 DATA30

43、 44 CYCLEOUT 69 VCC94 DATA10 20 DATA31 45 GND 70 GND 95 DATA11 21 GND 46 GND 71 MTEST0 96 VCC22 ADDR0 47 GND 72 MTEST1 97 DATA12 23 ADDR1 48 GRFEMP/ GPO0 73 MTEST2 98 DATA13 24 ADDR2 49 CYDNE/ GPO1 74 VCC99 DATA14 25 ADDR3 50 CYST/GPO2 75 Reserved 100 DATA15 FIGURE 3. Terminal connections. Provided

44、by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03611 REV B PAGE 11 NOTE: Following a CS assertion, there may be a maximum of 9 rising edges of BCLK before a CA is returned

45、. CA must be returned before another CS may be asserted. FIGURE 4. Timing waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03611 REV B PAGE 12 NOTE: Foll

46、owing a CS assertion, there may be a maximum of 9 rising edges of BCLK before a CA is returned. CA must be returned before another CS may be asserted. NOTE: There must be a minimum of 3 rising edges of BCLK between assertions of CS. FIGURE 4. Timing waveforms - Continued. Provided by IHSNot for Resa

47、leNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03611 REV B PAGE 13 NOTE: There must be a minimum of 3 rising edges of BCLK between assertions of CS. NOTES: 1. At the nth BCLK rising edge, DATAn is written into the FIFO. 2. CA is one cycle delay from respective CS. FIGURE 4. Timing waveforms - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFE