DLA DSCC-VID-V62 03620 REV A-2009 MICROCIRCUIT DIGITAL ADVANCED BIPOLAR CMOS 36-BIT BUS TRANSCEIVER WITH THREE-STATE OUTPUTS MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Update boilerplate paragraphs to current requirements. - PHN 09-02-17 Charles F. Saffle Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV A A A A A A A A A A A REV STATUS OF PAGES PAGE 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARE

2、D BY Thanh V. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Thanh V. Nguyen APPROVED BY Thomas M. Hess TITLE MICROCIRCUIT, DIGITAL, ADVANCED BIPOLAR CMOS, 36-BIT BUS TRANSCEIVER WITH THREE-STATE OUTPUTS, MONOLITHIC SILICON SIZE A CODE IDENT. NO.

3、 16236 DWG NO. V62/03620 YY-MM-DD 03-02-06 REV A PAGE 1 OF 11 AMSC N/A 5962-V040-09 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03620 REV A PAGE 2 1. SCOPE 1.

4、1 Scope. This drawing documents the general requirements of a high performance 36-bit bus transceiver with three-state outputs microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identificatio

5、n. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/03620 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01

6、74ABTH32245-EP 36-bit bus transceiver with three-state outputs 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 100 MS-026 Plastic quad flatpack 1.2.3 Lead finishes. The lead finishes are as specified below or other lead f

7、inishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUM

8、BUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03620 REV A PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to 7.0 V Input voltage range (VI) (except I/O ports) -0.5 V to 7.0 V 2/ Voltage range applied to any output in the high or power-off state (VO) -0.5 V to 5.5 V Cu

9、rrent into any output in the low state (IO). 96 mA Input clamp current (IIK) (VI 0) . -18 mA Output clamp current (IOK) (VO 0) -50 mA Storage temperature range (TSTG). -65C to 150C Package thermal impedance (JA): 3/ X package .50C/W 1.4 Recommended operating conditions. 4/ 5/ Supply voltage range (V

10、CC) . 4.5 V to 5.5 V Input voltage range (VI). 0.0 V to VCC Minimum high level input voltage (VIH) 2.0 V Maximum low level input voltage (VIL). 0.8 V Maximum high level output current (IOH) -24 mA Maximum low level output current (IOL) . 48 mA Maximum input transition rise or fall rate (t/v) (Output

11、s enabled) 10 ns/V Minimum power-up ramp rate (t/VCC) 200 s/V Operating free-air temperature range (TA). -55C to +125C 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at t

12、hese or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The input and output negative-voltage ratings may be exceeded if the input and output clam

13、p-current ratings are observed. 3/ The package thermal impedance is calculated in accordance with JESD 51-7. 4/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for pr

14、oduct used beyond the stated limits. 5/ Unused control pins must be held high or low to prevent them from floating. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62

15、/03620 REV A PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 - Registered and Standard Outlines for Semiconductor Devices JEDEC STD 51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Applications for copies should be addressed to the Electronic Industries Alliance,

16、2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS

17、 identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specif

18、ied in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1. 3.5.2 Truth table. The truth table shall

19、 be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. 3.5.4 Terminal connections. The terminal connections shall be as shown in figure 4. 3.5.5 Test circuit and timing waveforms. The test circuit and timing waveforms shall be as shown in figure 5. Provided b

20、y IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03620 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Limits Test Symbol Conditions VCC Temperature, TA Devi

21、ce type Min Max UnitInput clamp voltage VIK II= -18 mA 4.5 V 25C, -55C to 125C All -1.2 V IOH= -3 mA 4.5 V 2.5 IOH= -3 mA 5.0 V 3 High level output voltage VOH IOH= -24 mA 4.5 V25C, -55C to 125C All 2 V Low level output voltage VOL IOL= 48 mA 4.5 V 25C, -55C to 125C All 0.55 V Hysteresis (VT+- VT-)

22、Vhys 5.0 V 25C All 100 typical mV Control inputs All 1 Input current II VI= VCCor GND A or B ports 5.5 V 25C, -55C to 125C 20 A VI= 0.8 V All 100 Input bus hold current II(hold) VI= 2.0 V A or B ports 4.5 V 25C, -55C to 125C -100 A Three-state power-up current IOZPU2/ VO= 0.5 V to 2.7 V OE = X 0 V t

23、o 2.1 V25C, -55C to 125C All 50 A All Three-state power-down current IOZPD2/ VO= 0.5 V to 2.7 V OE = X 2.1 V to 0 V 25C, -55C to 125C 50 A High-state leakage current ICEX VO= 5.5 V Outputs high 5.5 V 25C, -55C to 125C All 50 A Output current IO3/ VO= 2.5 V 5.5 V 25C, -55C to 125C All -50 -180 mA Out

24、puts high 3 Outputs low All 20 Quiescent supply current ICC VI= VCCor GND IO= 0 A Output disabled 5.5 V 25C, -55C to 125C 2 mA Quiescent supply current delta, TTL input level ICC4/ One input at 3.4 V, other inputs at VCCor GND 5.5 V 25C, -55C to 125C All 1 mA Input capacitance CI VI= 2.5 V or 0.5 V

25、Control inputs 5.0 V 25C All 3.5 typical pF I/O capacitance CIO VO= 2.5 V or 0.5 V A or B ports 5.0 V 25C All 9.5 typical pF See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO

26、 SIZE A CODE IDENT NO. 16236 DWG NO. V62/03620 REV A PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Limits Test Symbol Conditions VCC Temperature, TA Device type Min Max UnittPLH 1 5.3 Propagation delay time, A to B or B to A tPHL 4.5 V to 5.5 V25C, -55C to 125C All 1 5.3 ns

27、tPZH 1 7.6 Propagation delay time, output enable, OE to B or A tPZL 4.5 V to 5.5 V25C, -55C to 125C All 1.5 8.2 ns tPHZ 0.8 6.7 Propagation delay time, output disable, OE to B or A tPLZ CL= 50 pF See figure 5 4.5 V to 5.5 V25C, -55C to 125C All 1 7.2 ns 1/ Testing and other quality control technique

28、s are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance i

29、s assured by characterization and/or design. 2/ This parameter is specified by characterization. 3/ Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 4/ This is the increase in supply current for each input that is at the specified TTL vo

30、ltage level rather than VCCor GND. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03620 REV A PAGE 7 Case X Dimensions Millimeters Millimeters Symbol Min Max Symb

31、ol Min Max A 1.60 D/E 15.80 16.20 A1 1.35 1.45 D1/E1 13.80 14.20 A2 0.25 D2/E2 12.00 TYP A3 0.05 e 0.50 BSC b 0.17 0.27 L 0.45 0.75 c 0.13 NOM NOTES: 1. All linear dimensions are in millimeters. 2. This case outline is subject to change without notice. 3. Fall within JEDEC MS-026. FIGURE 1. Case out

32、line. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03620 REV A PAGE 8 Each 9-bit section Inputs OE DIR Operation L L B data to A bus L H A data to B bus H X Iso

33、lation H = High voltage level L = Low voltage level X = Dont care FIGURE 2. Truth table. FIGURE 3. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/0

34、3620 REV A PAGE 9 Device type 01 Case outline X Terminal number Terminal symbol Terminal number Terminal symbol Terminal number Terminal symbol Terminal number Terminal symbol 1 1A9 26 4A2 51 4B1 76 1B8 2 2A1 27 4A3 52 3B9 77 1B7 3 GND 28 4A4 53 GND 78 1B6 4 2A2 29 GND 54 3B8 79 GND 5 2A3 30 4A5 55

35、3B7 80 1B5 6 2A4 31 4A6 56 3B6 81 1B4 7 2A5 32 4A7 57 3B5 82 1B3 8 GND 33 4A8 58 GND 83 1B2 9 2A6 34 4A9 59 3B4 84 1B1 10 2A7 35 GND 60 3B3 85 GND 11 2A8 36 4DIR 61 3B2 86 2DIR 12 2A9 37 4 OE 62 3B1 87 2 OE 13 VCC 38 VCC 63 VCC 88 VCC 14 3A1 39 3 OE 64 2B9 89 1 OE 15 3A2 40 3DIR 65 2B8 90 1DIR 16 3A

36、3 41 GND 66 2B7 91 GND 17 3A4 42 4B9 67 2B6 92 1A1 18 GND 43 4B8 68 GND 93 1A2 19 3A5 44 4B7 69 2B5 94 1A3 20 3A6 45 4B6 70 2B4 95 1A4 21 3A7 46 4B5 71 2B3 96 1A5 22 3A8 47 GND 72 2B2 97 GND 23 GND 48 4B4 73 GND 98 1A6 24 3A9 49 4B3 74 2B1 99 1A7 25 4A1 50 4B2 75 1B9 100 1A8 FIGURE 4. Terminal conne

37、ctions. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03620 REV A PAGE 10 NOTES: 1. CLincludes probe and jig capacitance. 2. Waveform 1 is for an output with int

38、ernal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 3. All input pulses are supplied by generators having the following characteristics:

39、PRR 10 MHz, ZO= 50 , tr 2.5 ns, tf 2.5 ns. 4. The outputs are measured one at a time with one input transition per measurement. FIGURE 5. Test circuit and timing waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMB

40、US COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03620 REV A PAGE 11 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper ha

41、ndling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for e

42、lectrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device manufa

43、cturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of sup

44、ply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number Top side marking V62/03620-01XE 01295 SN74ABTH32245MPZEP 74ABTH32245MEP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engi

45、neering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-