DLA DSCC-VID-V62 03640 REV C-2012 MICROCIRCUIT DIGITAL FIXED POINT DIGITAL SIGNAL PROCESSOR MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Add EP suffix to generic number and add package type designator to the vendor part number. - CFS 04-01-29 Thomas M. Hess B Correct lead finish for device 01. Update boilerplate. - CFS 05-11-01 Thomas M. Hess C Update boilerplate paragraphs to current requir

2、ements. - PHN 12-06-04 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV C C C C C C C C C C C C C PAGE 40 41 42 43 44 45 46 47 48 49 50 51 52 REV C C C C C C C

3、C C C C C C C C C C C C C C C PAGE 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 REV STATUS OF PAGES REV C C C C C C C C C C C C C C C C C PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 O

4、riginal date of drawing YY-MM-DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, FIXED POINT DIGITAL SIGNAL PROCESSOR, MONOLITHIC SILICON 03-12-01 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/03640 REV C PAGE 1 OF 52 AMSC N/A 5962-V063-12 Provided by IHSNot for ResaleNo

5、reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03640 REV C PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a fixed point digital signal processor, with an operating

6、 temperature range of -40C to +105C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/03640 01 X A Drawing De

7、vice type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). 1/ Device Generic number Circuit function 01 SM320C6202-EP Fixed point digital signal processor 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PU

8、B 95 Package style X 352 JEDEC MO-151/AAL-1 Plastic ball grid array 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladiu

9、m Z Other 1.3 Absolute maximum ratings. 2/ Supply voltage range, (CVDD) . -0.3 V to +2.3 V 3/ Supply voltage range, (DVDD) . -0.3 V to +4.0 V 3/ Input voltage range . -0.3 V to +4.0 V Output voltage range -0.3 V to +4.0 V Operating case temperature ranges, (TC): (A version) . -40C to +105C Storage t

10、emperature range, (TSTG) -65C to +150C Temperature cycle range, (1000 cycle performance) . -40C to +125C 1/ Users are cautioned to review the manufacturers data manual for additional user information relating to this device. 2/ Stresses beyond those listed under “absolute maximum rating” may cause p

11、ermanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device r

12、eliability. 3/ All voltage values are with respect to VSS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03640 REV C PAGE 3 Recommended operating conditions. Sup

13、ply voltage, Core (CVDD) +1.71 V to +1.89 V Supply voltage, I/O (DVDD) . +3.14 V to +3.46 V Supply ground (VSS) . 0.0 V High level input voltage, (VIH) . +2.0 V minimum Low level input voltage, (VIL) +0.8 V maximum High level output current, (IOH) . -8 mA maximum Low level output current, (IOL) . +8

14、 mA maximum Operating case temperature (TC) (A version) . -40C to +105C Junction to case (RJC) 0.47C/W Junction to free air (RJA): Air flow = 0.00 m/s 14.2C/W 4/ Air flow = 0.50 m/s 12.3C/W 4/ Air flow = 1.00 m/s 10.9C/W 4/ Air flow = 2.00 m/s 9.3C/W 4/ 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECH

15、NOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 3. REQUIREMENTS 3.1 Marking.

16、Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part n

17、umber and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction

18、, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.5.3 Block diagram. The block diagram shall be as specified on

19、 figure 3. 3.5.4 Load circuit. The load circuit shall be as specified on figure 4. 3.5.5 Timing waveforms. The timing waveforms shall be as specified on figure 5-43. 4/ m/s = Meters per second. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE

20、SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03640 REV C PAGE 4 TABLE I. Electrical performance characteristics. 1/ No. Test Symbol Test condition -40C TC+105C 1.71 V CVDD 1.89 V 3.14 V DVDD 3.46 V unless otherwise noted Limits Unit Min Max High level output voltage

21、 VOHDVDD= MIN, IOH= MAX 2.4 V Low level output voltage VOLDVDD= MIN, IOL= MAX 0.6 V Input current 2/ IIVI= VSSto DVDD10 A Off state output current IOZVO= DVDDor 0 V 10 A Supply current, CPU + CPU memory access 3/ IDD2VCVDD= NOM, CPU clock = 200 MHz 520 Typ mA Supply current, peripheral 3/ IDD2VCVDD=

22、 NOM, CPU clock = 200 MHz 390 Typ mA Supply current, I/O pins 3/ IDD3VDVDD= NOM, CPU clock = 200 MHz 70 Typ mA Input capacitance CI10 pF Output capacitance CO10 pF INPUT AND OUTPUT CLOCKS Timing requirements for CLKIN (PLL used) 4/ 5/ 6/ 1 Cycle time, CLKIN tc(CLKIN)See figure 8 5*M ns 2 Pulse durat

23、ion, CLKIN high tw(CLKINH)0.4C 3 Pulse duration, CLKIN low tw(CLKINL)0.4C 4 Transition time, CLKIN tt(CLKIN)5 Timing requirements for CLKIN PLL bypassed (x1) 4/ 7/ 1 Cycle time, CLKIN tc(CLKIN)See figure 8 5 ns 2 Pulse duration, CLKIN high tw(CLKINH)0.45C 3 Pulse duration, CLKIN low tw(CLKINL)0.45C

24、4 Transition time, CLKIN tt(CLKIN)0.6 Timing requirements for XCLKIN 8/ 1 Cycle time, XCLKIN tc(XCLKIN)See figure 9 4P ns 2 Pulse duration, XCLKIN high tw(XCLKINH)1.8P 3 Pulse duration, XCLKIN low tw(XCLKINL)1.8P Switching characteristics over recommended operating conditions for CLKOUT2 8/ 9/ 1 Cyc

25、le time, CLKOUT2 tc(CKO2)See figure 10 2P-0.7 2P+0.7 ns 2 Pulse duration, CLKOUT2 high tw(CKO2H)P-0.7 P+0.7 3 Pulse duration, CLKOUT2 low tw(CKO2L)P-0.7 P+0.7 Switching characteristics over recommended operating conditions for XFCLK 8/ 10/ 1 Cycle time, XFCLK tc(XFCLK)See figure 11 D*P-0.7 D*P+0.7 n

26、s 2 Pulse duration, XFCLK high tw(XFCLKH)(D/2)*P-0.7 (D/2)*P+0.7 3 Pulse duration, XFCLK low tw(XFCLKL)(D/2)*P-0.7 (D/2)*P+0.7 See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO S

27、IZE A CODE IDENT NO. 16236 DWG NO. V62/03640 REV C PAGE 5 TABLE I. Electrical performance characteristics - Continued. 1/ No. Test Symbol Test condition -40C TC+105C 1.71 V CVDD 1.89 V 3.14 V DVDD 3.46 V unless otherwise noted Limits Unit Min Max ASYNCHRONOUS MEMORY TIMING Timing requirements for as

28、ynchronous memory cycles 8/ 11/ 12/ 13/ 3 Setup time, EDx valid before ARE high tsu(EDV-AREH)See figure 12 and 13 1 ns 4 Hold time, EDx valid after ARE high th(AREH-EDV)3.5 6 Setup time, ARDY high before ARE low tsu(ARDYH-AREL)-(RST-3)*P-6 7 Hold time, ARDY high after ARE low th(AREL-ARDYH)(RST-3)*P

29、+2 9 Setup time, ARDY low before ARE low tsu(ARDYL-AREL)-(RST-3)*P-6 10 Hold time, ARDY low after ARE low th(AREL-ARDYL)(RST-3)*P+2 11 Pulse width, ARDY high tw(ARDYH)2P 15 Setup time, ARDY high before AWE low tsu(ARDYH-AWEL)-(WST-3)*P-6 16 Hold time, ARDY high after AWE low th(AWEL-ARDYH)(WST-3)*P+

30、2 18 Setup time, ARDY low before AWE low tsu(ARDYL-AWEL)-(WST-3)*P-6 19 Hold time, ARDY low after AWE low th(AWEL-ARDYL)(WST-3)*P+2 Switching characteristics over recommended operating conditions for asynchronous memory cycles 8/ 12/ 13/ 14/ 1 Output setup time, select signals valid to ARE low tosu(

31、SELV-AREL)See figure 12 and 13 RS*P-2 ns 2 Output hold time, ARE high to select signals invalid toh(AREH-SELIV)RH*P-2 5 Pulse width, ARE low tw(AREL)RST*P 8 Delay time, ARDY high to ARE high td(ARDYH-AREH)3P 4P+5 12 Output setup time, select signals valid to AWE low tosu(SELV-AWEL)WS*P-3 12 Output h

32、old time, AWE high to select signals invalid toh(AWEH-SELIV)WS*P-2 14 Pulse width, AWE low tw(AWEL)WST*P 17 Delay time, ARDY high to AWE high td(ARDYH-AWEH)3P 4P+5 SYNCHRONOUS-BURST MEMORY TIMING Timing requirements for synchronous-burst SRAM cycles for C6202 devices 7 Setup time, read EDx valid bef

33、ore CLKOUT2 high tsu(EDV-CKO2H)See figure 14 2.5 ns 8 Hold time, read Edx valid after CLKOUT2 high th(CKO2H-EDV)2.0 See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE

34、IDENT NO. 16236 DWG NO. V62/03640 REV C PAGE 6 TABLE I. Electrical performance characteristics Continued. 1/ No. Test Symbol Test condition -40C TC+105C 1.71 V CVDD 1.89 V 3.14 V DVDD 3.46 V unless otherwise noted Limits Unit Min Max SYNCHRONOUS-BURST MEMORY TIMING - Continued Switching characterist

35、ics over recommended operating conditions for synchronous-burst SRAM cycles for C6202 devices 8/ 15/ 1 Output setup time, CEx valid before CLKOUT2 high tosu(CEV-CKO2H)See figure 14 and 15 P-0.8 2 Output hold time, CEx valid after CLKOUT2 high toh(CKO2H-CEV)P-4 3 Output setup time, BEx valid before C

36、LKOUT2 high tosu(BEV-CKO2H)P-0.8 4 Output hold time, BEx invalid after CLKOUT2 high toh(CKO2H-BEIV)P-4 5 Output setup time, EAx valid before CLKOUT2 high tosu(EAV-CKO2H)P-0.8 6 Output hold time, EAx invalid after CLKOUT2 high toh(CKO2H-EAIV)P-4 9 Output setup time, SSADS/SDCAS valid before CLKOUT2 h

37、igh tosu(ADSV-CKO2H)P-0.8 10 Output hold time, SSADS/SDCAS valid after CLKOUT2 high toh(CKO2H-ADSV)P-4 11 Output setup time, SSOE/SDRAS valid before CLKOUT2 high 16/ tosu(OEV-CKO2H)P-0.8 12 Output hold time, SSOE/SDRAS valid after CLKOUT2 high toh(CKO2H-OEV)P-4 13 Output setup time, EDx valid before

38、 CLKOUT2 high 16/ tosu(EDV-CKO2H)P-1.2 14 Output hold time, EDx invalid after CLKOUT2 high toh(CKO2H-EDIV)P-4 15 Output setup time, SSWE/SDWE valid before CLKOUT2 high tosu(WEV-CKO2H)P-0.8 16 Output hold time, SSWE/SDWE valid after CLKOUT2 high toh(CKO2H-WEV)P-4 SYNCHRONOUS-DRAM TIMING Timing requir

39、ements for synchronous DRAM cycles for C6202 devices 7 Setup time, read EDx valid before CLKOUT2 high tsu(EDV-CKO2H)See figure 16 1.2 ns 8 Hold time, read EDx valid after CLKOUT2 high th(CKO2H-EDV)3.0 See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted wit

40、hout license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03640 REV C PAGE 7 TABLE I. Electrical performance characteristics Continued. 1/ No. Test Symbol Test condition -40C TC+105C 1.71 V CVDD 1.89 V 3.14 V DVDD 3.46 V unless otherwise noted L

41、imits Unit Min Max SYNCHRONOUS-DRAM TIMING - Continued Switching characteristics over recommended operating conditions for synchronous DRAM cycles for C6202 devices 8/ 15/ 1 Output setup time, CEx valid before CLKOUT2 high tosu(CEV-CKO2H)See figure 16-19 P-1 ns 2 Output hold time, CEx valid after CL

42、KOUT2 high toh(CKO2H-CEV)P-3.5 3 Output setup time, BEx valid before CLKOUT2 high tosu(BEV-CKO2H)P-1 4 Output hold time, BEx invalid after CLKOUT2 high toh(CKO2H-BEIV)P-3.5 5 Output setup time, EAx valid before CLKOUT2 high tosu(EAV-CKO2H)P-1 6 Output hold time, EAx invalid after CLKOUT2 high toh(CK

43、O2H-EAIV)P-3.5 9 Output setup time, SSADS/SDCAS valid before CLKOUT2 high tosu(CASV-CKO2H)P-1 10 Output hold time, SSADS/SDCAS valid after CLKOUT2 high toh(CKO2H-CASV)P-3.5 11 Output setup time, EDx valid before CLKOUT2 high 16/ tosu(EDV-CKO2H)P-1 12 Output hold time, EDx invalid after CLKOUT2 high

44、toh(CKO2H-EDIV)P-3.5 13 Output setup time, SSWE/SDWE valid before CLKOUT2 high tosu(WEV-CKO2H)P-1 14 Output hold time, SSWE/SDWE valid after CLKOUT2 high toh(CKO2H-WEV)P-3.5 15 Output setup time, SDA10 valid before CLKOUT2 high tosu(SDA10V-CKO2H)P-1 16 Output hold time, SDA10 invalid after CLKOUT2 h

45、igh toh(CKO2H-SDA10V)P-3.5 17 Output setup time, SSOE/SDRAS valid before CLKOUT2 high tosu(RASV-CKO2H)P-1 18 Output hold time, SSOE/SDRAS valid after CLKOUT2 high toh(CKO2H-RASV)P-3.5 See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from

46、 IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03640 REV C PAGE 8 TABLE I. Electrical performance characteristics Continued. 1/ No. Test Symbol Test condition -40C TC+105C 1.71 V CVDD 1.89 V 3.14 V DVDD 3.46 V unless otherwise noted Limits Unit Min Ma

47、x HOLD/HOLDA TIMING Timing requirements for the HOLDA/HOLD cycles 8/ 3 Output hold time, HOLD low after HOLDA low toh(HOLDAL-HOLDL)See figure 20 P ns Switching characteristics over recommended operating conditions for the HOLDA/HOLD cycles 8/ 17/ 1 Delay time, HOLD low to EMIF bus high impedance td(

48、HOLDL-EMHZ)See figure 20 3P 18/ ns 2 Delay time, EMIF bus high impedance to HOLDA low td(EMHZ-HOLDAL)0 2P 4 Delay time, HOLD high to EMIF bus low impedance td(HOLDH-EMLZ)3P 7P 5 Delay time, EMIF bus low impedance to HOLDA high td(EMLZ-HOLDAH)0 2P RESET TIMING Timing requirements for reset 8/ 1 Width of the RESET pulse (PLL stable) 19/ tw(RST)See figure 29 10P ns Width of the RESET pulse (PLL needs to sync up) 20/ 250 10 Setup time, XD configuration bits valid before RESET high 2