DLA DSCC-VID-V62 03641 REV A-2009 MICROCIRCUIT DIGITAL CONFIGURABLE MULTIPLE FUNCTION GATE MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Update boilerplate paragraphs to current requirements. - PHN 09-02-25 Charles F. Saffle Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV A A A A A A A A A A REV STATUS OF PAGES PAGE 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY

2、Phu H. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing YY-MM-DD CHECKED BY Phu H. Nguyen APPROVED BY Thomas M. Hess TITLE MICROCIRCUIT, DIGITAL, CONFIGURABLE MULTIPLE FUNCTION GATE, MONOLITHIC SILICON SIZE A CODE IDENT. NO. 16236 DWG NO. V62/03641 03-09-03 R

3、EV A PAGE 1 OF 10 AMSC N/A 5962-V043-09 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03641 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general r

4、equirements of a configurable multiple-function gate, with an operating temperature range of -40C to +85C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying

5、the item on the engineering documentation: V62/03641 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). 1/ Device Generic number Circuit function 01 SN74LVC1G98-EP Configurable multiple-function gate 1.2.2 Case outline(s). The case ou

6、tlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 6 JEDEC MO-203 Plastic small outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B T

7、in-lead plate C Gold plate D Palladium E Gold flash palladium Z Other _ 1/ Users are cautioned to review the manufacturers data manual for additional user information relating to these devices. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE

8、SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03641 REV A PAGE 3 1.3 Absolute maximum ratings. 2/ Supply voltage range, (VCC) . -0.5 V to +6.5 V Input voltage range, (VI) . -0.5 V to +6.5 V 3/ Voltage range applied to any output in the high-impedance or power-off sta

9、te, (VO) . -0.5 V to +6.5 V 3/ Voltage range applied to any output in the high or low state, (VO) -0.5 V to +6.5 V 3/ 4/ Input clamp current, (IIK) (VI 0) -50 mA Output clamp current, (IOK) (VO 0) . -50 mA Continuous output current, (IO) . 50 mA Continuous current through VCCor GND 100 mA Package th

10、ermal impedance, (JA) . +259C/W 5/ Storage temperature range, (TSTG) -65C to +150C 1.4 Recommended operating conditions. 6/ 7/ Min Max Unit Operating 1.65 5.5 Supply voltage VCCData retention only 1.5 V Input voltage VI0 5.5 V Output voltage VO0 VCCV VCC= 1.65 V -4 VCC= 2.3 V -8 -16 VCC= 3.0 V -24 H

11、igh level output current IOHVCC= 4.5 V -32 mA VCC= 1.65 V 4 VCC= 2.3 V 8 16 VCC= 3.0 V 24 Low level output current IOLVCC= 4.5 V 32 mA Operating ambient temperature TA-40 85 C _ 2/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress

12、 ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 3/ The input negative-voltage and o

13、utput voltage ratings may be exceeded if the input and output current ratings are observed. 4/ The value of VCCis provided in the recommended operating conditions table. 5/ The package terminal impedance is calculated in accordance with JESD 51-7. 6/ Use of this product beyond the manufacturers desi

14、gn rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 7/ All unused inputs of the device must be held at VCCor GND to ensure proper device operation. Refer to the manufacturer ap

15、plication report, Implications of Slow or Floating CMOS inputs, literature number SCBA004. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03641 REV A PAGE 4 2. AP

16、PLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices JEDEC STD 51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arling

17、ton, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.

18、2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I

19、herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as spec

20、ified on figure 2. 3.5.3 Logic diagram. The logic diagram shall be as specified on figure 3. 3.5.4 Logic configuration. The logic configuration shall be as specified on figure 4. 3.5.5 Load circuit and timing waveforms. The load circuit and timing waveforms shall be as specified on figure 5. Provide

21、d by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03641 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Limits Test Symbol Test conditions -40C TA +85C unl

22、ess otherwise specified VCCMin Max Unit 1.65 V 0.79 1.16 2.3 V 1.11 1.56 3.0 V 1.50 1.87 4.5 V 2.16 2.74 Positive-going input threshold voltage VT+5.5 V 2.61 3.33 V 1.65 V 0.39 0.62 2.3 V 0.58 0.87 3.0 V 0.84 1.14 4.5 V 1.41 1.79 Negative-going input threshold voltage VT-5.5 V 1.87 2.29 V 1.65 V 0.3

23、7 0.62 2.3 V 0.48 0.77 3.0 V 0.56 0.87 4.5 V 0.71 1.04 Hysteresis ( VT+- VT-) VT5.5 V 0.71 1.11 V IOH= -100 A 1.65 V to 5.5 V VCC 0.1 IOH= -4 mA 1.65 V 1.2 IOH= -8 mA 2.3 V 1.9 IOH= -16 mA 2.4 IOH= -24 mA 3.0 V 2.3 High level output voltage VOHIOH= -32 mA 4.5 V 3.8 V IOL= 100 A 1.65 V to 5.5 V 0.1 I

24、OL= 4 mA 1.65 V 0.45 IOL= 8 mA 2.3 V 0.3 IOL= 16 mA 0.4 IOL= 24 mA 3.0 V 0.55 Low level output voltage VOLIOL= 32 mA 4.5 V 0.55 V Input current IIVI= 5.5 V or GND 0 to 5.5 V 5 A Off-state leakage current IoffVIor VO= 5.5 V 0 10 A Quiescent supply current ICCVI= 5.5 V or GND, IO= 0 1.65 V to 5.5 V 10

25、 A Quiescent supply current delta ICCOne input at VCC 0.6, Other inputs at VCCor GND 3.0 V to 5.5 V 500 A Input capacitance CiVI= VCCor GND, TA= 25C 3.3 V 3.5 TYP pF 1.8 V 0.15 V 3.2 14.4 2.5 V 0.20 V 2.0 8.3 3.3 V 0.30 V 1.5 6.3 From any input to output Y tpd5.0 V 0.50 V 1.1 5.1 ns 1.8 V 23 TYP 2.5

26、 V 23 TYP 3.3 V 23 TYP Power dissipation capacitance Cpdf = 10 MHz, TA= 25C 5.0 V 26 TYP pF 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the ful

27、l temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENT

28、ER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03641 REV A PAGE 6 Case X Dimensions Millimeters Millimeters Symbol Min Max Symbol Min Max A 0.80 1.10 E 1.10 1.40 A1 0.00 0.10 E1 1.80 2.40 b 0.15 0.30 e 0.65 TYP c 0.13 NOM L 0.26 0.46 D 1.85 2.15 L1 0.15 TYP NOTES: 1. All linear

29、dimensions are in millimeters. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protrusions. 4. Falls within JEDEC MS-203. FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEF

30、ENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03641 REV A PAGE 7 Terminal number Terminal symbol 1 In1 2 GND 3 In0 4 Y 5 VCC6 In2 FIGURE 2. Terminal connections. Function table Inputs In2 In1 In0 Output Y L L L H L L H H L H L L L H H L H L L H H L H L H H L H H

31、 H H L FIGURE 3. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03641 REV A PAGE 8 Logic Function 2-to-1 data selector with inverter output 2-input

32、 NAND gate 2-input NOR gate with one inverted input 2-input AND gate with one inverted input 2-input NAND gate with one inverted input 2-input OR gate with one inverted input 2-input NOR gate Noninverted buffer Inverter FIGURE 4. Logic configuration. Provided by IHSNot for ResaleNo reproduction or n

33、etworking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03641 REV A PAGE 9 Test S1 Inputs tPLH/tPHLOpen VCCVItr/tfVMVLOADCLRLVtPLZ/tPZLVLOAD1.8 V 0.15 V VCC2 ns VCC/2 2 x VCC30 pF 1 k 0.15 V tPHZ/tPZHGND 2.5 V 0.20 V VCC

34、2 ns VCC/2 2 x VCC30 pF 500 0.15 V 3.3 V 0.30 V 3 V 2.5 ns 1.5 V 6 V 50 pF 500 0.3 V 5.0 V 0.50V VCC 2.5 ns VCC/2 2 x VCC 50 pF 500 0.3 V NOTES: 1. CLincludes probe and jig capacitance. 2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the ou

35、tput control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control 3. All input pulses are supplied by generators having following characteristics: PRR 10 MHz, ZO= 50 . 4. The outputs are measured one at a time with one transact

36、ion per measurement. 5. tPLZand tPHZare the same as tdis. 6. tPZLand tPZHare the same as ten. 7. tPLHand tPHLare the same as tpd. 8. All parameters and waveforms are not applicable to all devices. FIGURE 5. Load circuit and timing waveforms. Provided by IHSNot for ResaleNo reproduction or networking

37、 permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03641 REV A PAGE 10 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in t

38、heir internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in

39、accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient cha

40、racteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed a

41、s a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number 2/ Top-side marking V62/03641-01XE 01295 SN74LVC1G98IDCKREP CWR 1/ The vendor item drawing establishes an admin

42、istrative control number for identifying the item on the engineering documentation. 2/ The package is available taped and reeled. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-