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本文(DLA DSCC-VID-V62 03649 REV A-2009 MICROCIRCUIT DIGITAL ADVANCED HIGH SPEED CMOS OCTAL BUFFER DRIVER WITH 3-STATE OUTPUTS MONOLITHIC SILICON.pdf)为本站会员(周芸)主动上传,麦多课文库仅提供信息存储空间,仅对用户上传内容的表现方式做保护处理,对上载内容本身不做任何修改或编辑。 若此文所含内容侵犯了您的版权或隐私,请立即通知麦多课文库(发送邮件至master@mydoc123.com或直接QQ联系客服),我们立即给予删除!

DLA DSCC-VID-V62 03649 REV A-2009 MICROCIRCUIT DIGITAL ADVANCED HIGH SPEED CMOS OCTAL BUFFER DRIVER WITH 3-STATE OUTPUTS MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Update boilerplate paragraphs to current requirements. - PHN 09-03-16 Thomas M. Hess Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV A A A A A A A A A A A REV STATUS OF PAGES PAGE 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED B

2、Y Charles F. Saffle DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Charles F. Saffle APPROVED BY Thomas M. Hess TITLE MICROCIRCUIT, DIGITAL, ADVANCED HIGH SPEED CMOS, OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS, MONOLITHIC SILICON SIZE A CODE IDENT. NO. 16

3、236 DWG NO. V62/03649 YY-MM-DD 03-08-13 REV A PAGE 1 OF 11 AMSC N/A 5962-V051-09 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03649 REV A PAGE 2 1. SCOPE 1.1 Sc

4、ope. This drawing documents the general requirements of a high performance octal buffer/driver with 3-state outputs microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vend

5、or item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/03649 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 74AHC244-EP

6、 Octal buffer/driver with 3-state outputs 1.2.2 Case outlines. The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 20 JEDEC MO-153 Plastic small-outline Y 20 JEDEC MS-013 Plastic small-outline 1.2.3 Lead finishes. The lead finishes are as specified b

7、elow or other lead finishes as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CEN

8、TER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03649 REV A PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to +7.0 V Input voltage range (VI). -0.5 V to +7.0 V 2/ Output voltage range (VO) . -0.5 V to VCC+ 0.5 V 2/ Input clamp current (IIK) (VIVCC) 2

9、0 mA Continuous output current (IO) (VO= 0 to VCC) 25 mA Continuous current through VCCor GND. 50 mA Package thermal impedance (JA): X package . 83C/W 3/ Y package . 58C/W 3/ Storage temperature range (TSTG). -65C to +150C 1.4 Recommended operating conditions. 4/ 5/ Supply voltage range (VCC) . 2.0

10、V to 5.5 V Minimum high level input voltage (VIH): VCC= 2.0 V 1.5 V VCC= 3.0 V 2.1 V VCC= 5.5 V 3.85 V Maximum low level input voltage (VIL): VCC= 2.0 V 0.5 V VCC= 3.0 V 0.9 V VCC= 5.5 V 1.65 V Input voltage range (VI). 0.0 V to 5.5 V Output voltage range (VO) . 0.0 V to VCCMaximum high level output

11、 current (IOH): VCC= 2.0 V -50 A VCC= 3.3 V 0.3 V. -4.0 mA VCC= 5.0 V 0.5 V. -8.0 mA Maximum low level output current (IOL): VCC= 2.0 V 50 A VCC= 3.3 V 0.3 V. 4.0 mA VCC= 5.0 V 0.5 V. 8.0 mA Maximum input transition rise or fall rate (t/v): VCC= 3.3 V 0.3 V. 100 ns/V VCC= 5.0 V 0.5 V. 20 ns/V Operat

12、ing free-air temperature range (TA). -55C to +125C 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommende

13、d operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 3/ The package thermal impedance is calculated in ac

14、cordance with JESD 51-7. 4/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 5/ All unused inputs of the device must be held

15、 at VCCor GND to ensure proper device operation. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03649 REV A PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 - Register

16、ed and Standard Outlines for Semiconductor Devices JESD 51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.j

17、edec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall

18、be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physi

19、cal dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outlines. The case outlines shall be as shown in 1.2.2 and figure 1. 3.5.2 Truth table. The truth table shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as

20、 shown in figure 3. 3.5.4 Terminal connections. The terminal connections shall be as shown in figure 4. 3.5.5 Timing waveforms and test circuit. The timing waveforms and test circuit shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license f

21、rom IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03649 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Limits Test Symbol Conditions VCCTemperature TADevice Type Min Max Unit 2.0 V 1.9 3.0 V 2.9 IOH= -50 A 4.5 V 25C, -55C to 125C 4.4

22、 25C 2.58 IOH = -4 mA 3.0 V -55C to 125C 2.48 25C 3.94 High level output voltage VOHIOH= -8 mA 4.5 V -55C to 125C 01 3.80 V 2.0 V 0.1 3.0 V 0.1 IOL= 50 A 4.5 V 25C, -55C to 125C 0.1 25C 0.36 IOL = 4 mA 3.0 V -55C to 125C 0.5 25C 0.36 Low level output voltage VOLIOL= 8 mA 4.5 V -55C to 125C 01 0.5 V

23、25C 0.1 Input current II VI = 5.5 V or GND 0.0 V to 5.5 V -55C to 125C 01 1.0 25C 0.25 3-state output current IOZVO= VCCor GND, VI( OE )= VILor VIH5.5 V -55C to 125C 01 2.5 25C 4.0 Quiescent supply current ICCVI= VCCor GND IO= 0 A 5.5 V -55C to 125C 01 40.0 A Input capacitance CIVI= VCCor GND 5.0 V

24、25C 01 10 Output capacitance COVO= VCCor GND 5.0 V 25C 01 3.5 TYP Power dissipation capacitance CpdNo load, f = 1 MHz 5.0 V 25C 01 3.8 TYP pF Quiet output, maximum dynamic VOLVOL(P)2/ 5.0 V 25C 01 0.5 TYP V Quiet output, minimum dynamic VOLVOL(V)2/ 5.0 V 25C 01 -0.2 TYP V Quiet output, minimum dynam

25、ic VOHVOH(V)2/ 5.0 V 25C 01 4.8 TYP V High level dynamic input voltage VIH(D)2/ 5.0 V 25C 01 3.5 V Low level dynamic input voltage VIL(D)2/ CL= 50 pF 5.0 V 25C 01 1.5 V See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEF

26、ENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03649 REV A PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Limits Test Symbol Conditions VCCTemperature, TADevice type Min Max Unit 25C 8.4 3.0 V and 3.6 V -55C to 125C 1.0 10.0 25C 5.5 CL= 15

27、 pF See figure 5 4.5 V and 5.5 V -55C to 125C 01 1.0 6.5 25C 11.9 3.0 V and 3.6 V -55C to 125C 1.0 13.5 25C 7.5 Propagation delay time, A to Y tPLH, tPHLCL= 50 pF See figure 5 4.5 V and 5.5 V -55C to 125C 01 1.0 8.5 ns 25C 10.6 3.0 V and 3.6 V -55C to 125C 1.0 12.5 25C 7.3 CL= 15 pF See figure 5 4.5

28、 V and 5.5 V -55C to 125C 01 1.0 8.5 25C 14.1 3.0 V and 3.6 V -55C to 125C 1.0 16.0 25C 9.3 Propagation delay time, OE to Y tPZH, tPZLCL= 50 pF See figure 5 4.5 V and 5.5 V -55C to 125C 01 1.0 10.5 ns 25C 9.7 3.0 V and 3.6 V -55C to 125C 1.0 11.0 25C 7.2 CL= 15 pF See figure 5 4.5 V and 5.5 V -55C t

29、o 125C 01 1.0 8.5 25C 14.0 3.0 V and 3.6 V -55C to 125C 1.0 16.0 25C 9.2 Propagation delay time, OE to Y tPHZ, tPLZCL= 50 pF See figure 5 4.5 V and 5.5 V -55C to 125C 01 1.0 10.5 ns 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance

30、over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Characteristics are for

31、surface-mount packages only. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03649 REV A PAGE 7 Case X Dimensions Millimeters Inches Millimeters Inches Symbol Min

32、Max Min Max Symbol Min Max Min Max A - 1.20 - .047 E 4.30 4.50 .169 .177 A1 0.05 0.15 .002 .006 E1 6.20 6.60 .244 .260 b 0.19 0.30 .007 .012 e 0.65 NOM .026 NOM c 0.15 NOM .006 NOM L 0.50 0.75 .020 .030 D 6.40 6.60 .252 .260 NOTES: 1. This drawing is subject to change without notice. 2. Body dimensi

33、ons do not include mold flash or protrusion not to exceed 0.15 mm. 3. Falls within JEDEC MO-153. 4. All linear dimensions are shown in millimeters (inches). Inches equivalents are given for general information only. FIGURE 1. Case outlines. Provided by IHSNot for ResaleNo reproduction or networking

34、permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03649 REV A PAGE 8 Case Y Dimensions Millimeters Inches Millimeters Inches Symbol Min Max Min Max Symbol Min Max Min Max A - 2.65 - .104 E 7.39 7.59 .291 .299 A1 0.10 0.30 .0

35、04 .012 E1 10.15 10.65 .400 .419 b 0.35 0.51 .014 .020 e 1.27 NOM .050 NOM c 0.25 NOM .010 NOM L 0.40 1.27 .016 .050 D 12.70 12.95 .500 .510 NOTES: 1. This drawing is subject to change without notice. 2. Body dimensions do not include mold flash or protrusion not to exceed 0.006 inches (0.15 mm). 3.

36、 Falls within JEDEC MS-013. 4. All linear dimensions are shown in inches (millimeters). Metric equivalents are given for general information only. FIGURE 1. Case outlines - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CEN

37、TER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03649 REV A PAGE 9 (each 4-bit buffer/driver) Inputs OE A Output Y L H H L L L H X X X = Immaterial Z = High impedance state FIGURE 2. Truth table. FIGURE 3. Logic diagram. Device type 01 Case outline X, Y Terminal number Terminal

38、symbol Terminal number Terminal symbol 1 1 OE 11 2A1 2 1A1 12 1Y4 3 2Y4 13 2A2 4 1A2 14 1Y3 5 2Y3 15 2A3 6 1A3 16 1Y2 7 2Y2 17 2A4 8 1A4 18 1Y1 9 2Y1 19 2 OE 10 GND 20 VCCFIGURE 4. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,

39、-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03649 REV A PAGE 10 Notes: 1. CLincludes probe and jig capacitance. 2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is fo

40、r an output with internal conditions such that the output is high except when disabled by the output control. 3. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO= 50, tr 3 ns, tf 3 ns. 4. The outputs are measured one at a time with one input transition

41、per measurement. 5. For 3-state and Open Drain outputs tests: tPLH/tPHLS1 = Open tPLZ/tPZLS1 = VCCtPHZ/tPZHS1 = GND Open Drain S1 = VCCFIGURE 5. Timing waveforms and test circuit. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER,

42、 COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03649 REV A PAGE 11 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include pr

43、oper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practice

44、s for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device

45、 manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source

46、 of supply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number Top-Side Marking V62/03649-01XE 01295 SN74AHC244MPWREP AHC244EP V62/03649-01YE 01295 SN74AHC244MDWREP AHC244MEP 1/ The vendor item drawing establishes an administrative cont

47、rol number for identifying the item on the engineering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group 8505 Forest lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-

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