DLA DSCC-VID-V62 03652 REV A-2009 MICROCIRCUIT DIGITAL ADVANCED HIGH SPEED CMOS DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Update boilerplate paragraphs to current requirements. - PHN 09-05-27 Thomas M. Hess Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Charles F. Saffle

2、 DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Charles F. Saffle TITLE MICROCIRCUIT, DIGITAL, ADVANCED HIGH SPEED CMOS, DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET, MONOLITHIC SILICON YY-MM-DD 03-08-19 APPROVED BY Thomas M. Hess

3、 SIZE A CODE IDENT. NO. 16236 DWG NO. V62/03652 REV A PAGE 1 OF 12 AMSC N/A 5962-V058-09 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03652 REV A PAGE 2 1. SCO

4、PE 1.1 Scope. This drawing documents the general requirements of a high performance dual positive-edge-triggered D-type flip-flop with clear and preset microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is

5、the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/03652 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Gen

6、eric Circuit function 01 74AHC74-EP Dual positive-edge-triggered D-type flip-flop with clear and preset 1.2.2 Case outlines. The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 14 JEDEC MO-153 Plastic small-outline Y 14 JEDEC MS-012 Plastic small-out

7、line 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or netwo

8、rking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03652 REV A PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to +7.0 V Input voltage range (VI) . -0.5 V to +7.0 V 2/ Output voltage range (V

9、O) . -0.5 V to VCC+ 0.5 V 2/ Input clamp current (IIK) (VIVCC) 20 mA Continuous output current (IO) (VO= 0 to VCC) 25 mA Continuous current through VCCor GND 50 mA Package thermal impedance (JA): X package . 113C/W 3/ Y package . 86C/W 3/ Storage temperature range (TSTG) -65C to +150C 1.4 Recommende

10、d operating conditions. 4/ 5/ Supply voltage range (VCC) . 2.0 V to 5.5 V Minimum high level input voltage (VIH): VCC= 2.0 V 1.5 V VCC= 3.0 V 2.1 V VCC= 5.5 V 3.85 V Maximum low level input voltage (VIL): VCC= 2.0 V 0.5 V VCC= 3.0 V 0.9 V VCC= 5.5 V 1.65 V Input voltage range (VI) . 0.0 V to 5.5 V O

11、utput voltage range (VO) . 0.0 V to VCCMaximum high level output current (IOH): VCC= 2.0 V -50 A VCC= 3.3 V 0.3 V . -4.0 mA VCC= 5.0 V 0.5 V . -8.0 mA Maximum low level output current (IOL): VCC= 2.0 V 50 A VCC= 3.3 V 0.3 V . 4.0 mA VCC= 5.0 V 0.5 V . 8.0 mA Maximum input transition rise or fall rat

12、e (t/v): VCC= 3.3 V 0.3 V . 100 ns/V VCC= 5.0 V 0.5 V . 20 ns/V Operating free-air temperature range (TA) -55C to +125C 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at t

13、hese or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The input and output voltage ratings may be exceeded if the input and output current ratin

14、gs are observed. 3/ The package thermal impedance is calculated in accordance with JESD 51-7. 4/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyo

15、nd the stated limits. 5/ All unused inputs of the device must be held at VCCor GND to ensure proper device operation. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V

16、62/03652 REV A PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 - Registered and Standard Outlines for Semiconductor Devices JESD 51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Applications for copies should be addressed to the Electronic Industries Alliance, 250

17、0 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS id

18、entification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified

19、 in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outlines. The case outlines shall be as shown in 1.2.2 and figure 1. 3.5.2 Truth table. The truth table shall be as

20、shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. 3.5.4 Terminal connections. The terminal connections shall be as shown in figure 4. 3.5.5 Timing waveforms and test circuit. The timing waveforms and test circuit shall be as shown in figure 5. Provided by IHSNo

21、t for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03652 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions VCCTemperature, TADevice type Limits U

22、nit Min Max High level output voltage VOHIOH= -50 A 2.0 V 25C, -55C to 125C 01 1.9 V 3.0 V 2.9 4.5 V 4.4 IOH= -4 mA 3.0 V 25C 2.58 -55C to 125C 2.48 IOH= -8 mA 4.5 V 25C 3.94 -55C to 125C 3.80 Low level output voltage VOLIOL= 50 A 2.0 V 25C, -55C to 125C 01 0.1 V 3.0 V 0.1 4.5 V 0.1 IOL= 4 mA 3.0 V

23、25C 0.36 -55C to 125C 0.5 IOL= 8 mA 4.5 V 25C 0.36 -55C to 125C 0.5 Input current, A or B inputs IIVI= 5.5 V or GND 0.0 V to 5.5 V 25C 01 0.1 A -55C to 125C 1.0 Quiescent supply current ICCVI= VCCor GND IO= 0 A 5.5 V 25C 01 2.0 A -55C to 125C 20.0 Input capacitance CIVI= VCCor GND 5.0 V 25C 01 10 pF

24、 Power dissipation capacitance CpdNo load f = 1 MHz 5.0 V 25C 01 32 TYP pF Quiet output, maximum dynamic VOLVOL(P)2/ CL= 50 pF 5.0 V 25C 01 0.8 V Quiet output, minimum dynamic VOLVOL(V)2/ 5.0 V 25C 01 -0.8 V Quiet output, minimum dynamic VOHVOH(V)2/ 5.0 V 25C 01 4.7 V High level dynamic input voltag

25、e VIH(D)2/ 5.0 V 25C 01 3.5 V Low level dynamic input voltage VIL(D)2/ 5.0 V 25C 01 1.5 V See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO.

26、 V62/03652 REV A PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions VCCTemperature, TADevice type Limits Unit Min Max Maximum clock frequency fmaxCL= 15 pF 3.0 V and 3.6 V 25C 01 80 MHz -55C to 125C 70 4.5 V and 5.5 V 25C 130 -55C to 125C 110 CL= 50 pF 3.0

27、V and 3.6 V 25C 50 -55C to 125C 45 4.5 V and 5.5 V 25C 90 -55C to 125C 75 Propagation delay time, PRE or CLR to Q or Q tPLH, tPHLCL= 15 pF See figure 5 3.0 V and 3.6 V 25C 01 12.3 ns -55C to 125C 1.0 14.5 4.5 V and 5.5 V 25C 7.7 -55C to 125C 1.0 9.0 CL= 50 pF See figure 5 3.0 V and 3.6 V 25C 15.8 -5

28、5C to 125C 1.0 18.0 4.5 V and 5.5 V 25C 9.7 -55C to 125C 1.0 11.0 Propagation delay time, CLK to Q or Q tPLH, tPHLCL= 15 pF See figure 5 3.0 V and 3.6 V 25C 01 11.9 ns -55C to 125C 1.0 14.0 4.5 V and 5.5 V 25C 7.3 -55C to 125C 1.0 8.5 CL= 50 pF See figure 5 3.0 V and 3.6 V 25C 15.4 -55C to 125C 1.0

29、17.5 4.5 V and 5.5 V 25C 9.3 -55C to 125C 1.0 10.5 See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03652 REV A PAGE 7 TABLE I. Electr

30、ical performance characteristics - Continued. 1/ Test Symbol Conditions VCCTemperature, TADevice type Limits Unit Min Max Pulse duration twPRE or CLR low See figure 5 3.0 V and 3.6 V 25C 01 6.0 ns -55C to 125C 7.0 4.5 V and 5.5 V 25C 5.0 -55C to 125C 5.0 CLK See figure 5 3.0 V and 3.6 V 25C 6.0 -55C

31、 to 125C 7.0 4.5 V and 5.5 V 25C 5.0 -55C to 125C 5.0 Setup time before CLK tsuData See figure 5 3.0 V and 3.6 V 25C 01 6.0 ns -55C to 125C 7.0 4.5 V and 5.5 V 25C 5.0 -55C to 125C 5.0 PRE or CLR inactive See figure 5 3.0 V and 3.6 V 25C 5.0 -55C to 125C 5.0 4.5 V and 5.5 V 25C 3.0 -55C to 125C 3.0

32、Hold time, data after CLK thSee figure 5 3.0 V and 3.6 V 25C 01 0.5 ns -55C to 125C 0.5 4.5 V and 5.5 V 25C 0.5 -55C to 125C 0.5 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not

33、 necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Characteristics are for surface-mount packages only. Provided by IHSNot for R

34、esaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03652 REV A PAGE 8 Case X Dimensions Symbol Millimeters Inches Symbol Millimeters Inches Min Max Min Max Min Max Min Max A - 1.20 - .047 E

35、4.30 4.50 .169 .177 A1 0.05 0.15 .002 .006 E1 6.20 6.60 .244 .260 b 0.19 0.30 .007 .012 e 0.65 NOM .026 NOM c 0.15 NOM .006 NOM L 0.50 0.75 .020 .030 D 4.90 5.10 .193 .201 NOTES: 1. This drawing is subject to change without notice. 2. Body dimensions do not include mold flash or protrusion not to ex

36、ceed 0.15 mm. 3. Falls within JEDEC MO-153. 4. All linear dimensions are shown in millimeters (inches). Inches equivalents are given for general information only. FIGURE 1. Case outlines. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY

37、 CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03652 REV A PAGE 9 Case Y Dimensions Symbol Millimeters Inches Symbol Millimeters Inches Min Max Min Max Min Max Min Max A - 1.75 - .069 E 3.81 4.00 .150 .157 A1 0.10 0.25 .004 .010 E1 5.80 6.20 .228 .244 b 0.35 0.51 .014 .020

38、e 1.27 NOM .050 NOM c 0.20 NOM .008 NOM L 0.40 1.12 .016 .044 D 8.55 8.75 .337 .344 NOTES: 1. This drawing is subject to change without notice. 2. Body dimensions do not include mold flash or protrusion not to exceed 0.006 inches (0.15 mm). 3. Falls within JEDEC MS-012. 4. All linear dimensions are

39、shown in inches (millimeters). Metric equivalents are given for general information only. FIGURE 1. Case outlines - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236

40、DWG NO. V62/03652 REV A PAGE 10 (each flip-flop) Inputs Outputs PRE CLR CLK D Q Q L H X X H L H L X X L H L L X X H* H* H H H H L H H L L H H H L X QOQ O X = Immaterial = Rising edge of CLK * = This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (hig

41、h) level. FIGURE 2. Truth table. FIGURE 3. Logic diagram. Device type 01 Case outlines: X and Y Terminal number Terminal symbol Terminal number Terminal symbol 1 1 CLR 8 2 Q 2 1D 9 2Q 3 1CLK 10 2 PRE 4 1 PRE 11 2CLK 5 1Q 12 2D 6 1 Q 13 2 CLR 7 GND 14 VCCFIGURE 4. Terminal connections. Provided by IH

42、SNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03652 REV A PAGE 11 Notes: 1. CLincludes probe and jig capacitance. 2. Waveform 1 is for an output with internal conditions such

43、that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 3. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO= 50, tr

44、3 ns, tf 3 ns. 4. The outputs are measured one at a time with one input transition per measurement. 5. For 3-state and Open Drain outputs tests: tPLH/tPHLS1 = Open tPLZ/tPZLS1 = VCCtPHZ/tPZHS1 = GND Open Drain S1 = VCCFIGURE 5. Timing waveforms and test circuit. Provided by IHSNot for ResaleNo repro

45、duction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03652 REV A PAGE 12 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requireme

46、nts as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and

47、 marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggeste